PI7C7300DNA datasheet(35/107 Pages) PERICOM

35 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 35 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

00000

0000 0000 0000 0001

00001

0000 0000 0000 0010

00010

0000 0000 0000 0100

00011

0000 0000 0000 1000

00100

0000 0000 0001 0000

00101

0000 0000 0010 0000

00110

0000 0000 0100 0000

00111

0000 0000 1000 0000

01000

0000 0001 0000 0000

01001

0000 0010 0000 0000

01010

0000 0100 0000 0000

01011

0000 1000 0000 0000

01100

0001 0000 0000 0000

01101

0010 0000 0000 0000

01110

0100 0000 0000 0000

01111

1000 0000 0000 0000

10h – 1Eh

10000 – 11110

0000 0000 0000 0000

1Fh

11111

Generate special cycle (P_AD[7:2] = 00h)

0000 0000 0000 0000 (P_AD[7:2] = 00h)

PI7C7300D can assert up to 16 unique address lines to be used as IDSEL signals for up

to 16 devices on the secondary bus, for device numbers ranging from 0 through 15.

Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals

should not be necessary. However, if device numbers greater than 15 are desired, some

external method of generating IDSEL lines must be used, and no upper address bits are

then asserted. The configuration transaction is still translated and passed from the

primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the

transaction ends in a master abort.

PI7C7300D forwards Type 1 to Type 0 configuration read or write transactions as

delayed transactions. Type 1 to Type 0 configuration read or write transactions are

limited to a single 32-bit data transfer.

4.8.3

TYPE 1 TO TYPE 1 FORWARDING

Type 1 to Type 1 transaction forwarding provides a hierarchical configuration

mechanism when two or more levels of PCI-to-PCI bridges are used.

When PI7C7300D detects a Type 1 configuration transaction intended for a PCI bus

downstream from the secondary bus, PI7C7300D forwards the transaction unchanged to

the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration

command or to a special cycle transaction by a downstream PCI-to-PCI bridge.

Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met

during the address phase:

The lowest two address bits are equal to 01b.

The bus number falls in the range defined by the lower limit (exclusive) in the

secondary bus number register and the upper limit (inclusive) in the subordinate bus

number register.

The bus command is a configuration read or write transaction.

PI7C7300DNA Datasheet(PDF) 35 Page - Pericom Semiconductor Corporation

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