PI7C7300DNA datasheet(88/107 Pages) PERICOM

88 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 88 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

14.1.34

UPSTREAM (S1 or S2 to P) MEMORY LIMIT UPPER 32 BITS

Bit

Function

Type

Description

31:0

Upstream

Memory Limit

Address

R/W

Defines bits [63:32] of the upstream memory limit

Reset to 0

14.1.35

P_SERR# EVENT DISABLE REGISTER – OFFSET 64h

Bit

Function

Type

Description

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

Posted Write

Parity Error

R/W

Controls PI7C7300D’s ability to assert P_SERR# when it is unable to

transfer any read data from the target after 2

24 attempts.

0: P_SERR# is asserted if this event occurs and the SERR# enable bit

in the command register is set.

1: P_SERR# is not assert if this event occurs.

Reset to 0

Posted Write

Non-Delivery

R/W

Controls PI7C7300D’s ability to assert P_SERR# when it is unable to

transfer delayed write data after 2

24 attempts.

0: P_SERR# is asserted if this event occurs and the SERR# enable bit

in the command register is set

1: P_SERR# is not asserted if this event occurs

Reset to 0

Target Abort

During Posted

Write

R/W

Controls PI7C7300D’s ability to assert P_SERR# when it receives a

target abort when attempting to deliver posted write data.

0: P_SERR# is asserted if this event occurs and the SERR# enable bit

in the command register is set

1: P_SERR# is not asserted if this event occurs

Reset to 0

Master Abort On

Posted Write

R/W

Controls PI7C7300D’s ability to assert P_SERR# when it receives a

master abort when attempting to deliver posted write data.

0: P_SERR# is asserted if this event occurs and the SERR# enable bit

in the command register is set

1: P_SERR# is not asserted if this event occurs

Reset to 0

Delayed Write

Non-Delivery

R/W

Controls PI7C7300D’s ability to assert P_SERR# when it is unable to

transfer delayed write data after 2

24 attempts.

0: P_SERR# is asserted if this event occurs and the SERR# enable bit

in the command register is set

1: P_SERR# is not asserted if this event occurs

Reset to 0

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