PI7C7300DNA datasheet(26/107 Pages) PERICOM

26 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 26 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

bytes of write data with valid byte enable bits are compared. If any of the byte enable bits

are turned off (driven HIGH), the corresponding byte of write data is not compared.

If the initiator repeats the write transaction before the data has been transferred to the

target, PI7C7300D returns a target retry to the initiator. PI7C7300D continues to return a

target retry to the initiator until write data is delivered to the target, or until an error

condition is encountered. When the write transaction is repeated, PI7C7300D does not

make a new entry into the delayed transaction queue. Section 4.9.3.1 provides detailed

information about how PI7C7300D responds to target termination during delayed write

transactions.

PI7C7300D implements a discard timer that starts counting when the delayed write

completion is at the head of the delayed transaction completion queue. The initial value

of this timer can be set to the retry counter register offset 78h.

If the initiator does not repeat the delayed write transaction before the discard timer

expires, PI7C7300D discards the delayed write completion from the delayed transaction

completion queue. PI7C7300D also conditionally asserts P_SERR# (see Section 7.4).

4.6.4

WRITE TRANSACTION ADDRESS BOUNDARIES

PI7C7300D imposes internal address boundaries when accepting write data. The aligned

address boundaries are used to prevent PI7C7300D from continuing a transaction over a

device address boundary and to provide an upper limit on maximum latency. PI7C7300D

returns a target disconnect to the initiator when it reaches the aligned address boundaries

under conditions shown in Table 4–3.

Table 4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES

Type of Transaction

Condition

Aligned Address Boundary

Delayed Write

All

Disconnects after one data transfer

Posted Memory Write

Memory write disconnect control

bit = 0

(1)

4KB aligned address boundary

Posted Memory Write

Memory write disconnect control

bit = 1

(1)

Disconnects at cache line boundary

Posted Memory Write and

Invalidate

Cache line size

≠ 1, 2, 4, 8, 16

4KB aligned address boundary

Posted Memory Write and

Invalidate

Cache line size = 1, 2, 4, 8, 16

Cache line boundary if posted memory

write data FIFO does not have enough

space for the cache line

Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the

configuration space.

4.6.5

BUFFERING MULTIPLE WRITE TRANSACTIONS

PI7C7300D continues to accept posted memory write transactions as long as space for at

least one DWORD of data in the posted write data buffer remains. If the posted write

data buffer fills before the initiator terminates the write transaction, PI7C7300D returns a

target disconnect to the initiator.

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