PI7C7300DNA datasheet(67/107 Pages) PERICOM

67 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 67 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

9.1

PRIMARY PCI BUS ARBITRATION

PI7C7300D implements a request output pin, P_REQ#, and a grant input pin, P_GNT#,

for primary PCI bus arbitration. PI7C7300D asserts P_REQ# when forwarding

transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at

least one pending transaction resides in the queues in the upstream direction, either

posted write data or delayed transaction requests, PI7C7300D keeps P_REQ# asserted.

However, if a target retry, target disconnect, or a target abort is received in response to a

transaction initiated by PI7C7300D on the primary PCI bus, PI7C7300D de-asserts

P_REQ# for two PCI clock cycles.

For all cycles through the bridge, P_REQ# is not asserted until the transaction request

has been completely queued. When P_GNT# is asserted LOW by the primary bus arbiter

after PI7C7300D has asserted P_REQ#, PI7C7300D initiates a transaction on the

primary bus during the next PCI clock cycle. When P_GNT# is asserted to PI7C7300D

when P_REQ# is not asserted, PI7C7300D parks P_AD, P_CBE, and P_PAR by driving

them to valid logic levels. When the primary bus is parked at PI7C7300D and

PI7C7300D has a transaction to initiate on the primary bus, PI7C7300D starts the

transaction if P_GNT# was asserted during the previous cycle.

9.2

SECONDARY PCI BUS ARBITRATION

PI7C7300D implements an internal secondary PCI bus arbiter. This arbiter supports eight

external masters on secondary 1 and seven external masters on secondary 2 in addition to

PI7C7300D. The internal arbiter can be disabled, and an external arbiter can be used

instead for secondary bus arbitration.

9.2.1

SECONDARY BUSARBITRATION USING THE INTERNAL

ARBITER

To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied

LOW. PI7C7300D has eight/seven secondary bus 1/2 request input pins, S1_REQ#[7:0],

S2_REQ#[6:0], and has eight/seven secondary bus 1/2 output grant pins, S1_GNT#[7:0],

S2_GNT#[6:0], to support external secondary bus masters. The secondary bus request

and grant signals are connected internally to the arbiter and are not brought out to

external pins when S_CFN# is HIGH.

The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with

each set taking care of 8 requests/ grants. Each set of masters can be assigned to a high

priority group and a low priority group. The low priority group as a whole represents one

entry in the high priority group; that is, if the high priority group consists of n masters,

then in at least every n+1 transactions the highest priority is assigned to the low priority

group. Priority rotates evenly among the low priority group. Therefore, members of the

high priority group can be serviced n transactions out of n+1, while one member of the

low priority group is serviced once every n+1 transactions. Error! Reference source not

found. shows an example of an internal arbiter where four masters, including

PI7C7300D, are in the high priority group, and five masters are in the low priority group.

Using this example, if all requests are always asserted, the highest priority rotates among

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