PI7C7300DNA datasheet(56/107 Pages) PERICOM

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PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 56 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

PI7C7300D sets the primary interface parity-error-detected bit in the status register.

Because there was not an exact data and parity match, the write status is not returned

and the transaction remains in the queue.

Similarly, for upstream delayed write transactions, when the parity error is detected on

the initiator bus and PI7C7300D has write status to return, the following events occur:

PI7C7300D first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two

cycles later, if the secondary interface parity-error-response bit is set in the bridge

control register (offset 3Ch).

PI7C7300D sets the secondary interface parity-error-detected bit in the secondary

status register.

Because there was not an exact data and parity match, the write status is not returned

and the transaction remains in the queue.

For downstream transactions, where the parity error is being passed back from the target

bus and the parity error condition was not originally detected on the initiator bus, the

following events occur:

PI7C7300D asserts P_PERR# two cycles after the data transfer, if the following are

both true:

The parity-error-response bit is set in the command register of the primary

interface.

The parity-error-response bit is set in the bridge control register of the

secondary interface.

PI7C7300D completes the transaction normally.

For upstream transactions, when the parity error is being passed back from the target bus

and the parity error condition was not originally detected on the initiator bus, the

following events occur:

PI7C7300D asserts S_PERR# two cycles after the data transfer, if the following are

both true:

The parity error response bit is set in the command register of the primary

interface.

The parity error response bit is set in the bridge control register of the secondary

interface.

PI7C7300D completes the transaction normally.

7.2.4

POSTED WRITE TRANSACTIONS

During downstream posted write transactions, when PI7C7300D responds as a target, it

detects a data parity error on the initiator (primary) bus and the following events occur:

PI7C7300D asserts P_PERR# two cycles after the data transfer, if the parity error

response bit is set in the command register of primary interface.

PI7C7300D sets the parity error detected bit in the status register of the primary

interface.

PI7C7300D captures and forwards the bad parity condition to the secondary bus.

PI7C7300D completes the transaction normally.

PI7C7300DNA Datasheet(PDF) 56 Page - Pericom Semiconductor Corporation

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