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PI7C7300DNA Datasheet(PDF) 61 Page - Pericom Semiconductor Corporation

Part # PI7C7300DNA
Description  3-PORT PCI-to-PCI BRIDGE
PDF  107 Pages
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI7C7300DNA Datasheet(HTML) 61 Page - Pericom Semiconductor Corporation

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PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 61 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Table 7-6 shows assertion of S_PERR# that is set under the following conditions:
PI7C7300D is either the target of a write transaction or the initiator of a read
transaction on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
PI7C7300D detects a data parity error on the secondary bus or detects P_PERR#
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.



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