PI7C7300DNA datasheet(52/107 Pages) PERICOM

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PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 52 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

6.4

DATA SYNCHRONIZATION

Data synchronization refers to the relationship between interrupt signaling and data

delivery. The PCI Local Bus Specification, Revision 2.2, provides the following

alternative methods for synchronizing data and interrupts:

The device signaling the interrupt performs a read of the data just written (software).

The device driver performs a read operation to any register in the interrupting device

before accessing data written by the device (software).

System hardware guarantees that write buffers are flushed before interrupts are

forwarded.

PI7C7300D does not have a hardware mechanism to guarantee data synchronization for

posted write transactions. Therefore, all posted write transactions must be followed by a

read operation, either from the device to the location just written (or some other location

along the same path), or from the device driver to one of the device registers.

ERROR HANDLING

PI7C7300D checks, forwards, and generates parity on both the primary and secondary

interfaces. To maintain transparency, PI7C7300D always tries to forward the existing

parity condition on one bus to the other bus, along with address and data. PI7C100

always attempts to be transparent when reporting errors, but this is not always possible,

given the presence of posted data and delayed transactions.

To support error reporting on the PCI bus, PI7C7300D implements the following:

PERR# and SERR# signals on both the primary and secondary interfaces

Primary status and secondary status registers

The device-specific P_SERR# event disable register

This chapter provides detailed information about how PI7C7300D handles errors. It also

describes error status reporting and error operation disabling.

7.1

ADDRESS PARITY ERRORS

PI7C7300D checks address parity for all transactions on both buses, for all address and

all bus commands. When PI7C7300D detects an address parity error on the primary

interface, the following events occur:

If the parity error response bit is set in the command register, PI7C7300D does not

claim the transaction with P_DEVSEL#; this may allow the transaction to terminate

in a master abort. If parity error response bit is not set, PI7C7300D proceeds

normally and accepts the transaction if it is directed to or across PI7C7300D.

PI7C7300D sets the detected parity error bit in the status register.

PI7C7300D asserts P_SERR# and sets signaled system error bit in the status register,

if both the following conditions are met:

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