PI7C7300DNA datasheet(94/107 Pages) PERICOM

94 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 94 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

14.1.53

CAPABILITY ID REGISTER – OFFSET C0h

Bit

Function

Type

Description

7:0

Capability ID for

Hot Swap

R/O

Capability ID for Hot Swap

00h: Reserved

01h: PCI Power Management (PCIPM)

02h: Accelerated Graphics Port (AGP)

03h: Vital Product Data (VPD)

04h: Slot Identification (SI)

05h: Message Signaled Interrupts (MSI)

06h: Compact PCI Hot Swap (CHS)

07h – 255h: Reserved

Reset to 06h

14.1.54

NEXT POINTER REGISTER – OFFSET C0h

Bit

Function

Type

Description

15:8

Next Pointer

R/O

00: End of pointer (00h).

14.1.55

HOT SWAP CONTROL AND STATUS REGISTER – OFFSET C0h

Bit

Function

Type

Description

Not Available

R/O

Not used. Returns 0 when read. Reset to 0

ENUM Signal

Mask

R/W

0: Mask ENUM# signal

1: Enable ENUM# signal

Not Available

R/O

Not used. Returns 0 when read. Reset to 0

LED ON/OFF

R/W

LOO signal (LED on/off)

0: LED on

1: LED off

Reset to 0

21:20

Not Available

R/O

Not Used. Returns 0 when read. Reset to 0

ENUM# Status –

Extraction

R/W

0: ENUM# asserted

1: ENUM# not asserted

Reset to 0

ENUM# Status –

Insertion

R/W

0: ENUM# asserted

1: ENUM# not asserted

Reset to 0

31:24

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

BRIDGE BEHAVIOR

A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number

of possibilities. Those possibilities are summarized in the table below:

PI7C7300DNA Datasheet(PDF) 94 Page - Pericom Semiconductor Corporation

PI7C7300DNA Datasheet(HTML) 94 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL