PI7C7300DNA datasheet(87/107 Pages) PERICOM

87 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 87 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

Bit

Function

Type

Description

30:28

Secondary Bus

Master

Preemption

Control

R/W

Sets the number of clocks for time-to-preempt after another master

request.

000: 32 clocks

001: 8 clocks

010: 16 clocks

011: 64 clocks

100: 128 clocks

Reset to 000

Preemption

R/W

Sets preemption.

0: preemption ON

1: preemption OFF

Reset to 0

14.1.31

UPSTREAM (S1 or S2 to P) MEMORY BASE REGISTER –

OFFSET 50h

Bit

Function

Type

Description

3:0

64 bit addressing

R/O

0: 32 bit addressing

1: 64 bit addressing

Reset to 1

15:4

Upstream

Memory Base

Address

R/W

Controls upstream memory base address.

Reset to 00000000h

14.1.32

UPSTREAM (S1 or S2 to P) MEMORY LIMIT REGISTER –

OFFSET 50h

Bit

Function

Type

Description

19:16

64 bit addressing

R/O

0: 32 bit addressing

1: 64 bit addressing

Reset to 1

31:20

Upstream

Memory Limit

Address

R/W

Controls upstream memory limit address.

Reset to 000FFFFFh

14.1.33

UPSTREAM (S1 or S2 to P) MEMORY BASE UPPER 32-BITS

Bit

Function

Type

Description

31:0

Upstream

Memory Base

Address

R/W

Defines bits [63:32] of the upstream memory base

Reset to 0

PI7C7300DNA Datasheet(PDF) 87 Page - Pericom Semiconductor Corporation

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