PI7C7300DNA datasheet(70/107 Pages) PERICOM

70 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 70 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

the secondary bus. If the internal arbiter is disabled, PI7C7300D parks the secondary bus

only when the reconfigured grant signal, S_REQ#[0], is asserted and the secondary bus is

idle.

COMPACT PCI HOT SWAP

Compact PCI (cPCI) Hot Swap (PICMG 2.1, R1.0) defines a process for installing and

removing PCI boards form a Compact PCI system without powering down the system.

The PI7C7300D is Hot Swap Friendly silicon that supports all the cPCI Hot Swap

Capable features and adds support for Software Connection Control. Being Hot Swap

Friendly, the PI7C7300D supports the following:

Compliance with PCI Specification 2.2

Tolerates VCC from Early Power

Asynchronous Reset

Tolerates Precharge Voltage

I/O Buffers Meet Modified V/I Requirements

Limited I/O Pin Leakage at Precharge Voltage

When the PI7C7300D resides on the Compact PCI add-in card, the Primary Bus must be

the bus that is inserted into the Compact PCI system. To perform the Hot Swap function,

the device must be configured according to the CPCI Hot-Swap Specifications. For the

PI7C7300D, the only path for configuration is through the Primary Bus. The bridge may

not be configured through either secondary buses. If the user chooses to use the

secondary buses for insertion, an external register needs to be provided for the Hot Swap

Control Status Register.

CLOCKS

This chapter provides information about the clocks.

11.1

PRIMARY CLOCK INPUTS

PI7C7300D implements a primary clock input for the PCI interface. The primary

interface is synchronized to the primary clock input, P_CLK, and the secondary interface

is synchronized to the secondary clock. The secondary clock is derived internally from

the primary clock, P_CLK, through an internal PLL. PI7C7300D operates at a maximum

frequency of 66 MHz.

11.2

SECONDARY CLOCK OUTPUTS

PI7C7300D has 16 secondary clock outputs, S_CLKOUT[15:0] that can be used as clock

inputs for up to fifteen external secondary bus devices. The S_CLKOUT[15:0] outputs

are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by

a minimum of 0ns. This is the rule for using secondary clocks:

PI7C7300DNA Datasheet(PDF) 70 Page - Pericom Semiconductor Corporation

PI7C7300DNA Datasheet(HTML) 70 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL