PI7C7300DNA datasheet(81/107 Pages) PERICOM

81 / 107 page

PI7C7300D

3-PORT PCI-TO-PCI BRIDGE

Page 81 of 107

Pericom Semiconductor

November 2005 - Revision 1.01

Bit

Function

Type

Description

Signaled Target

Abort

R/WC

Set to 1 (by a target device) whenever a target abort cycle occurs on

its secondary (S1 or S2) interface

Reset to 0

Received Target

Abort

R/WC

Set to 1 (by a master device) whenever transactions on its secondary

(S1 or S2) interface are terminated with target abort

Reset to 0

Received Master

Abort

R/WC

Set to 1 (by a master) when transactions on its secondary (S1 or S2)

interface are terminated with Master Abort

Reset to 0

Received System

Error

R/WC

Set to 1 when S1_SERR# or S2_SERR# is asserted

Reset to 0

Detected Parity

Error

R/WC

Set to 1 when address or data parity error is detected on the

secondary (S1 or S2) interface

Reset to 0

14.1.17

MEMORY BASE REGISTER – OFFSET 20h

Bit

Function

Type

Description

3:0

R/O

Lower four bits of register are read only and return 0.

Reset to 0

15:4

Memory Base

Address [15:4]

R/W

Defines the bottom address of an address range for the bridge to

determine when to forward memory transactions from one interface

to the other. The upper 12 bits correspond to address bits [31:20]

and are writable. The lower 20 bits corresponding to address bits

[19:0] are assumed to be 0.

Reset to 0

14.1.18

MEMORY LIMIT REGISTER – OFFSET 20h

Bit

Function

Type

Description

19:16

R/O

Lower four bits of register are read only and return 0.

Reset to 0

31:20

Memory Limit

Address [31:20]

R/W

Defines the top address of an address range for the bridge to

determine when to forward memory transactions from one interface

to the other. The upper 12 bits correspond to address bits [31:20]

and are writable. The lower 20 bits corresponding to address bits

[19:0] are assumed to be FFFFFh.

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