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PI7C7300DNA Datasheet(PDF) 42 Page - Pericom Semiconductor Corporation |
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PI7C7300DNA Datasheet(HTML) 42 Page - Pericom Semiconductor Corporation |
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42 / 107 page ![]() PI7C7300D 3-PORT PCI-TO-PCI BRIDGE Page 42 of 107 Pericom Semiconductor November 2005 - Revision 1.01 When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. Otherwise, the transaction is discarded from the buffers. 4.9.4.2 TARGET DISCONNECT PI7C7300D returns a target disconnect to an initiator when one of the following conditions is met: PI7C7300D hits an internal address boundary. PI7C7300D cannot accept any more write data. PI7C7300D has no more read data to deliver. See Section 4.6.4 for a description of write address boundaries, and Section 4.7.3 for a description of read address boundaries. 4.9.4.3 TARGET ABORT PI7C7300D returns a target abort to an initiator when one of the following conditions is met: PI7C7300D is returning a target abort from the intended target. When PI7C7300D returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface. 4.10 CONCURRENT MODE OPERATION The Bridge can be configured to run in concurrent operation. Concurrent operation is defined as cycles going from one device on one secondary bus to another device on the same or other secondary bus. This off-loads traffic from the primary bus, allowing other traffic to run on the primary bus concurrently. The Bridge is already configured to handle concurrent operation. However, the devices themselves need to be configured to do so. Meaning, device drivers for the specific device used will have to be configured to perform the operation. Please see section 5.1 for more information on addressing. 5 ADDRESS DECODING PI7C7300D uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support. |
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