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DP83924 Datasheet(PDF) 41 Page - National Semiconductor (TI) |
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DP83924 Datasheet(HTML) 41 Page - National Semiconductor (TI) |
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41 / 42 page ![]() 7.0 AC and DC Electrical Specifications (Continued) 41 www.national.com 7.2.15 AUI Collision Specifications 7.2.16 Network Test Loads Note: The 40 Ω load is the effective differential resistance seen by the TXU pins during normal operation. P lease see Figure6 which shows a 1: 2transformer for the TXU pins. Since a 100 Ω load on the other side of a 1:2 transformer looks like a 25Ω load to the TXU side of the transformer, the equivalent differential resistance seen by the transmitting port is = 10.5//Zc + 25 + 10.5//Zc ~= 40 Ω where Zc is the impedance of the 1000 pf capacitors. For 10BASE-T frequencies between 5 MHz and 10 MHz this impedance varies between 32 to 16 Ω in // with the 10.5 Ω resistors. 7.2.17 AC Timing Test Condition Symbol Parameter Min Max Units t49 Collision Turn On Delay (CD ± to COL) 600 ns t50 Collision Turn Off Delay (CD ± to COL) 900 ns Figure 15. Attachment Unit Interface Load for ATE testing Figure 16. Twisted Pair Interface Load for ATE testing Reference Limits Input Levels (Digital Pins, tR = tF = 3ns) 0 V - 3.0 V Input/Output Reference Levels (Digital Pins) 1.5 V Differential Input Reference Levels 2.0 Vpp Differential Input/Output Reference Levels 50% of Differential CD± COL t49 t50 27 uH 78 Ω TX+ TX- TX OutputTest Load 40a Ω TXU+ TXU- |
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