DP83924 datasheet(10/42 Pages) NSC

10 / 42 page

2.0 Interface Descriptions (Continued)

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In addition to the compatibility mode options, the recovered

clock (RXC) is selectable for 5 RXCs after the deassertion

of carrier sense (CRS) or for continuous RXCs after the

deassertion of CRS. This is programmable through the

serial MII or through the COL[4] strapping option only when

the device is in the NSC mode.

2.3 LED Interface

The LED interface consists of two modes. The first option,

normal LED mode, requires an external 8-bit shift register.

During every LED update cycle, 8-bits are shifted out to the

external shift registers. This allows two LEDs per port. One

LED indicates activity (TX or RX) and the second indicates

port status (per Table 8). The status LEDs will blink at dif-

ferent rates depending on the associated ports status.If a

port experiences both Bad Polarity and Link Lost, then the

LEDs will go to the fast blink state (i.e. Link Lost). Port

activity and status are shifted out port 1 first. The LED

update rate is every 50ms. The LED clock rate is 1MHz. All

port activity is extended to 50ms to make it visible. Data is

valid on the rising edge of LED_CLK and is active low.

Refer to Figur e4

The second option, enhanced LED mode, serially shifts a

16-bit stream out of the 4TPHY. This option outputs per

port data for RX, TX, Full Duplex (FDX), and LinkCoded

status. These four bits per port can be used to support two

LEDs. One is a bi-color LED (decode of the FDX and Link-

Coded bits) to indicate LINK status and duplex status as

shown in Table 9. The second LED indicates activity (TX or

RX). As with the first LED option, port 1 status is shifted out

first and the data is active low. Refer to F igure5 for the tim-

ing sequence

To select the desired LED mode, the COL [1] pin has a

strapping feature. If COL[1] is a logic ‘0’ during reset, then

“enhanced” LED mode is enabled. If COL[1] is a logic ‘1’

during reset, then “normal” LED mode is enabled

(Application note:) During the update cycle data coming out

of the shift register is not going to be valid until the cycle is

completed and all the bits are shifted in place. These out-

puts should not be used to directly control a MAC unless

the shift register outputs are latched during the update

cycle. See Section 5.3 o n page28.

2.4 Network Interface

2.4.1 Twisted Pair Interface

The Quad 10Mb/s Transceiver provides two buffered and

filtered 10Base-T transmit outputs (for each port) that are

connected to the output isolation transformer via two

impedance matching resistor/capacitor networks. See

Figur e6. The twisted pair receiver implements an intelli-

gent receive squelch on the RXI+ differential inputs to

ensure that impulse noise on the receive inputs will not be

mistaken for a valid signal. This smart squelch circuitry

(which is described in detail under the Functional Descrip-

tion) employs a combination of amplitude and timing mea-

surements to determine the validity of data on the twisted

pair inputs. Only after these conditions have been satisfied

will Carrier Sense (CRS) be generated to indicate that valid

data is present.

2.4.2 Attachment Unit Interface

A single port (port 1) on the transceiver has a separate

(non- multiplexed) AUI interface. This interface is a full

802.3 standard AUI interface capable of driving the full 50m

cable. The schematic for connecting this interface to the

AUI connector is shown in Fi gure7.

Figure 3. NRZ Interface Timing Diagram (NSC mode)

COL

TXC

TXE

TXD

Setup

Hold

5 Clocks

RXC

CRS

RXD

Setup

Hold

Transmit Interface SIgnals

Receive Interface Signals

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