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This register controls the various operating modes available for the transceiver and ENDEC functions. There is one reg-

ister per ENDEC/Transceiver on this device.

Table 12. Port N Control/Status Register, addr = 00h - 03h (port 1 to port 4)

D15

D14

D13

D12

D11

D10 : D9

D8

D7

D6 : D3

D2

D1

D0

RST

LPBK

LNKPLS

FDX

JABE

RESV

LNKDIS

ERR

RESV

POLST

LNK ST

JAB ST

Name

Bit

Reset

Value

Description

Type

RST

D15

0

Software Reset/Enable: If this bit is set to ‘1’, then this port’s transceiv-

ers and ENDEC modules are reset back to their idle state (IEEE state

diagram idle state, i.e. it will reestablish link, re auto-negotiate). If this bit

is ‘0’, then normal operation is expected. Software reset doesn’t sample

the strap options. (See Sec tion3.3 .15 on page16) This bit is self clear-

ing.

R/W

LPBK

D14

0

Loopback Transceiver: If this bit is set, then this port’s 10base-T trans-

ceiver will loop data from near the network interface pins back to the

MAC, to test the operation of the transceiver. If reset, loopback is dis-

abled.

R/W

LINKPLS

D13

0

Link pulse transmission: Transmission of Link Pulses can be turned

off by setting this bit to ‘1’. If this bit is set to ‘0’, normal operation (Link

Pulse Transmission Enabled) is resumed.

R/W

FDX

D12

Opposite of

the strap

option

FDX[4:1]

Full Duplex Operation: If this bit is ‘1’, then the ports full duplex capa-

bility is enabled. If ‘0’, then half-duplex is enabled. The reset value is de-

termined by the mode selected by the FDX[4:1] pins and is opposite of

the strap value. (i.e. if strap FDX=’1’ then reset value of this bit = ‘0’)

R/W

JABE

D11

1

Jabber Enable: If this bit is set, then the ports jabber function is en-

abled. If reset, then the jabber feature is disabled.

R/W

resv

D10-9

0

Reserved: must be written with ‘0’.

R/W

LNKDIS

D8

0

Link Detect Disable: If this bit is set, this port’s link detection circuitry

will be disabled and regardless of the link condition, good_link will be es-

tablished. If reset, then normal link operation is enabled.

R/W

ERR

D7

0

LED Error: If this bit is set, this port’s status LED will go solid. If reset,

normal LED operation is resumed.This bit can be set by management

entity based on any criteria and will be used only as a visual prompt. The

status LED is only available during normal LED mode of operation.

R/W

resv

D6-3

0

Reserved: must be written with ‘0’.

R/W

POL ST

D2

1

Polarity Status: This bit is set when bad polarity has been detected.

Status bit, read-only. This bit is only meaningful if ENPOLSW bit D9 of

register 08h has been set.

R

LNK ST

D1

1

Link Status: This bit is set, when the port is in the link-fail state. (Even

in forced AUI mode on port 1, this bit will still indicate TPI link status for

port1). If link detect is disabled by setting bit D8 above, then this bit is

always = 0 (good link state).

R

JAB ST

D0

0

Jabber Status: This bit is set, when the port is in the jabber condition.

Status bit, read-only. This bit is always = 0 (no jabber condition) if bit

D11 above is reset (jabber disabled).

R