DP83924 datasheet(16/42 Pages) NSC

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3.0 Detailed Functional Description (Continued)

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pins will not take affect until a device reset is performed. A

logic ‘0’ enables full duplex and a logic’1’ enables simplex

mode. In addition, the full duplex capability of a port can

also be changed dynamically by writing the FDX bit (D12)

of the Port Control Register via the Mgmt Interface.

The second option (enhanced FDX mode), allows chang-

ing the full duplex configuration of each port

dynamically

through the FDX[4:1] pins. As soon as the logic state on

the FDX[4:1] pins are changed, the corresponding ports full

duplex mode will be enabled or disabled.

In order to select the desired full duplex mode, the COL[2]

pin has a strapping feature. The default is normal full

duplex mode. If enhanced full duplex mode is desired, then

a 2.7K pull-down resistor is required on the COL[2] pin.

During device reset, the COL[2] pin is sampled to deter-

mine the correct full duplex mode configuration.

Regardless of the full duplex mode, the logic state of the

FDX[4:1] pins are sampled during reset to determine a

port’s initial configuration for full duplex capability.

3.3.15 Strapping Options and Reset

Tabl e10 shows the various strapping options and the asso-

ciated pins used to configure the device at power-up.

These pins are sampled during device reset.(Power up or

hardware reset, but not software port reset.)These pins

have internal pull-ups, if the default modes are desired, no

external resistors are required. (Except FDX[4:1] which

have no pull-up resistors.) A 2.7 k

Ω pull down resistor(s)

are required to select non-default modes. If some type of

Figure 10. Receive Clock Timing - Continuous RXC Mode vs. 5 RXC Mode

a. There will be a transition period where the RXC switches from the internal clock to received clock.

b. There are 5 RXCs after CRS is deasserted

c. There are no RXCs after CRS is deasserted. ple as e see Table7 on page11

CRS

RXCb

RXCa

345

RXCc

RXD

Table 10. Strapping Option Description (Default = ‘1’, except FDX[4:1] pins have no default)

Pin Name

Function

‘1’

‘0’

Comments

COL[4]

Gate RXC

5 RXCs

Continuous Selects the # of RXCs after CRS deassertion

COL[3]

Rx Filter Select

Disable

Enable

Enables/disables the Rx filter. Suggest en-

able

COL[2]

Full Duplex Mode Select

Normal

Enhanced

Selects normal or enhanced full duplex mode

COL[1]

LED Mode Select

Normal

Enhanced

Selects normal or enhanced LED mode

CRS[3:1]

Transceiver Address Select

Addr

Sets the Tcvr address for MII access

FDX[4:1]

Per Port Full Duplex Select

Half duplex Full Duplex Selects full or half duplex configuration per

port (no internal pull-ups)

RXD[4]

Auto-Negotiation Enable

Disable

Enable

Enables/disables Auto-Negotiation.

RXD[3:1]

LNK[1]

Programmable MAC Interface

Mode 1

See Tab le7

on page11

Selects one of five MAC interface modes.

See the table in the MAC interface section.

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