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3.0 Detailed Functional Description (Continued)

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3.5.23 ID_Code Instruction

The ID_Code instruction allows users to select the 32-bit

IDCODE register and interrogate the contents which

consist of the manufacturer's ID, part ID and the version

number. For DP83924B the ID code register holds the

value h’1800801F.

3.5.24 Bypass Instruction

The bypass instruction uses the bypass register. The

bypass register contains a single shift-register stage and is

used to provide a minimum length serial path between the

TDI and TDO pins of the DP83924B when test operation is

not required. This allows more rapid movement of test data

to and from other testable devices in the system.

3.5.25 Sample/Preload Instruction

The Sample/Preload instruction allows scanning of the

boundary-scan register without causing interference to the

normal operation of the on-chip system logic.

Two functions are performed when this instruction is

selected.

Sample allows a snapshot to be taken of the data flowing

from the system pins to the on-chip test logic or vice versa,

without interfering with normal operation. The snapshot is

taken on the rising edge of TCK in the Capture-DR

controller state, and the data can be viewed by shifting

through the component's TDO output.

While sampling and shifting data out through TDO for

observation, preload allows an initial data pattern to be

shifted in through TDI and to be placed at the latched

parallel output of the boundary-scan register cells which

are connected to system output pins. This ensures that

known data is driven through the system output pins upon

entering the Extest instruction.

Without Preload, indeterminate data would be driven until

the first scan sequence has been completed. The shifting

of data for the Sample and Preload phases can occur

simultaneously. While data capture is being shifted out, the

preload data can be shifted in.

3.5.26 Extest Instruction

The Extest instruction allows circuitry external to the

DP83924B (typically the board interconnections) to be

tested.

Prior to executing the Extest instruction, the first test

stimulus to be applied will be shifted into the boundary-

scan registers using the Sample/Preload instruction. Thus,

when the change to the Extest instruction takes place,

known data will be driven immediately from the DP83924B

to its external connections.

This provides stimulus to the system input pins of adjacent

devices on the assembled printed circuit board s. Figure12

below illustrates the IEEE 1149.1 architecture.

3.5.27 Device Testing

IEEE 1149.1 provides a simple solution for testing many of

the standard static pin parametrics. Reasonably accurate

limits may be tested as a functional pattern.

The IEEE 1149.1 test circuitry is tested itself as a

consequence of testing pin parametrics. Specific tests are:

TRI-STATE® conditions of TDO when serial shift

between TDI and TDO is not selected

Input leakage of TCK, TMS, TDI and TRST

Output has TRI-STATE leakage of TDO

Opens and shorts of TCK, TMS, TDI,TRST, and TDO

IDCODE register, the bypass registerand the TAP

controller state machine sequences

Open and shorted pins can be identified by placing an

alternating bit pattern on the I/O pins. Any shorted bond

wires would either cause an input to be misinterpreted in

the inputs scan phase, or the test comparator would fail an

output during data scan.

Repeating the test with the inverse bit pattern provides

coverage of VCC and GND short/open circuits.

3.5.28 Boundary Scan Description Language File

A Boundary Scan Description Language (BSDL) file is

available. Contact your local National Semiconductor

representative to obtain the latest version.

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