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2.0 Interface Descriptions

Interface Overview

The 4TPHY’s interfaces can be categorized into the follow-

ing groups of signals:

1. Management Interface - Allows host to read status and

set operating modes

2. Media Access Control Interface - Straight forward NRZ

interface to Ethernet MACs

3. LED Interface - Serial LED interface to off chip shift reg-

isters

4. Network Interfaces - Integrated 10BASE-T and AUI.

5. Clock - Allows connection of an external clock module.

2.1 Management Interface

This interface is a simple serial interface that is modeled

after the MII standard serial interface, though it does not

adhere to the MII standard completely (the protocol is fol-

lowed, but the register space is not). The interface signals

consist of a clock and data line for transfer of data to and

from the registers.

In a multiple 4TPHY system, it is necessary to distinguish

between the devices in order to access the correct regis-

ters for configuration and status information. This is accom-

plished by assigning each 4TPHY a unique transceiver

address. The lower 3 bits of the transceiver address,

T[2:0], is latched in during reset based on the logic state of

CRS[3:1]. The upper 2 bits of the transceiver address,

T[4:3], must be zero. Therefore, 32 ports can be supported

with a single MII bus.

The register address field indicates which register within

the 4TPHY that is to be accessed (read or write).

During a write operation, all 32 bits are driven onto MDIO

by the host, indicating which transceiver and register the

data is to be written.

During a read operation, the first 14 bits are driven onto

MDIO by the host, then the bus is released, allowing the

4TPHY to drive the requested data onto MDIO.

The serial lines do not require any preamble on these pins,

however if it is provided it is ignored so long as the 0110 or

0101 pattern is not present. If a continuous MDC is not

supplied, then at the end of each command (read or write),

2 additional MDCs are required in order to allow the inter-

nal state machine to transition back to it’s idle state. Refer

to Figur e2.

2.2 MAC Interface

This interface connects the ENDEC/Transceiver to an

Ethernet MAC controller. This interface consists of a serial

data transmit interface and a serial receive interface. The

interface clocks data out (on receive) or in (on transmit) on

the rising edge of the clock. Refer t o Figure3. Most stan-

dard 10Mb/s controllers use this interface but they may dif-

fer in the polarity of the signals or on what edge of

TXCs/RXCs that data is clocked in. In the default mode

(NSC/TI mode), all signals are active high with rising edge

sampling.

The 4TPHY utilizes a programmable MAC digital interface

which enables it to directly interface to standard controllers

from National Semiconductor, TI, AMD, Seeq, Fujitsu, and

Intel. The compatibility modes are selected either by soft-

ware via the Global Control/Status Register or by hardware

strap options on pins RXD[3:1].See Table 7 below.

Figure 2. Serial Management Interface Time Diagram (read/write)

00

1

1

A3

A4

T3

T4

0

Z

D0

D15

MDC

MDIO

Register Read

Register Write

Note 1: The management interface addressing includes a 5 bit field for the Transceiver Address, T[4:0], and a 5 bit field for the register

address, A[4:0]. The MII assumes the transceiver address applies to a si ngle port, but in this implementation a single address

refers to a single IC. The transceiver address is set by 3 external pins, CRS[3:1]. T[4:3] must be zero to address the transceiver.

Thus up to 32 10BASE-T ports can be addressed from a single interface (8 addr x 4 ports/addr).

T1

T2

T0

A1

A2

A0

1

2

3

4

5

6

7

8

9

1011

12

1314

15

1617

31

32

prefix

read

transceiver address

register address

turn

data

around

01

0

1

A3

A4

T3

T4

0

1

D0

D15

MDIO

T1

T2

T0

A1

A2

A0

prefix

write

transceiver address

register address

turn

data

around

33

34

Note 2: Two MDCs (clocks 33, 34) are required after each read or write in order to allow the internal state machine to transition back t o

it’s IDLE state.