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ATMEGA88 Datasheet(PDF) 83 Page - ATMEL Corporation |
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ATMEGA88 Datasheet(HTML) 83 Page - ATMEL Corporation |
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83 / 349 page  83 ATmega48/88/168 2545D–AVR–07/04 Pin Change Interrupt Flag Register - PCIFR • Bit 7..3 - Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 2 - PCIF2: Pin Change Interrupt Flag 2 When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 1 - PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 0 - PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. Pin Change Mask Register 2 – PCMSK2 • Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16 Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corre- sponding I/O pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding I/O pin is disabled. Pin Change Mask Register 1 – PCMSK1 • Bit 7 – Res: Reserved Bit This bit is an unused bit in the ATmega48/88/168, and will always read as zero. • Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8 Each PCINT14..8-bit selects whether pin change interrupt is enabled on the correspond- ing I/O pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt Bit 7 654 32 10 – – – – – PCIF2 PCIF1 PCIF0 PCIFR Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65432 1 0 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 00000 0 0 Bit 7 65432 1 0 – PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 00000 0 0 |
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