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ATMEGA88 Datasheet(PDF) 18 Page - ATMEL Corporation |
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ATMEGA88 Datasheet(HTML) 18 Page - ATMEL Corporation |
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18 / 349 page  18 ATmega48/88/168 2545D–AVR–07/04 minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 22 for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be fol- lowed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. The EEPROM Address Register – EEARH and EEARL • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 256/512/512 bytes EEPROM space. The EEPROM data bytes are addressed lin- early between 0 and 255/511/511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. EEAR8 is an unused bit in ATmega48 and must always be written to zero. The EEPROM Data Register – EEDR • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read oper- ation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. The EEPROM Control Register – EECR • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write opera- Bit 151413121110 9 8 –––– ––– EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7654 321 0 Read/Write R RRRR RR R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 X XX XXX XXX Bit 7654 321 0 MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 Bit 7654 3 2 1 0 – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 |
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