Arbitration Controller Internal Register Bit Changes

TABLE III Restricted Mode Arbitration or Unrestricted Mode Arbitration

(One Pass or Second Pass of Two Pass)

Modules Category

during Arbitration

TXCN1

RR

(Note 1)

All Bits

STATE

STATUS

RXCN0

All Bits

RXCN1

RXMSG

A(07)

Reset Set

CLRERI

Reset Set

CLRMGI

CLRPFI

(Note 2)

W

C

M

U(04) RR PO P1

Competitor

5

X

1 2 0 1

5

3

3

3

3

3

X 4

X 5

By-Stander

5

X

1

0

5

3

3

3

3

3

X 4

X 5

Sending Message

X

1 2 0 1

3

X 4

X 5

Receiving Message

X

1

0 1

3

X 4

X 5

Pre-Emption

X

3

3

3

3

IBA

5

X

5

3

3

3

3

3

X 4

X 5

(Note 4)

(Note 5)

Parking

(Note 3)

Note

The number shown within the box defines the arbitration phase where the particular bit may change state

Note 1

Note that the STATE Register is updated in each Phase of Arbitration

Note 2

This is the new Masters Competition Number

Note 3

Parking is only a Phase 0 event

Note 4

The RR bit is only updated on the New Master

Note 5

The M bit is updated if IBA succeeded during Restricted Mode or Unrestricted Mode (One Pass or the First Pass of Two Pass Arbitration)

‘‘X’’ means that any Phase can update this bit (or bits)

‘‘’’ is used in the table to depict the condition where a particular Status bit is Reset and where it is Set (Ex 0 1 means that this Status bit is Reset in Phase 0 and

Set in Phase 1)

‘‘–’’ is used in the table to depict the condition where a particular Status bit may change within several sequential phases (Ex 2–4 means that this Status bit can

change in Phases 2 3 or 4)

TABLE IV Unrestricted Mode First Pass of Two Pass Arbitration

Modules Category

during Arbitration

TXCN1

RR

(Note 1)

All Bits

State

Status

(Note 2)

RXCN0

All Bits

RXCN1

RXMSG

A(07)

Reset Set

CLRERI

Reset Set

CLRMGI

CLRPFI

W

C

M

U(04)

RR

PO

P1

Competitor

X

1 2

0 1

3

X 4

X 5

By-Stander

X

1

0

3

X 4

X 5

Sending Message

X

1 2

0 1

X 4

X 5

Receiving Message

X

1

0 1

X 4

X 5

Pre-emption

X

3

IBA

X

5

3

X 4

X 5

Parking (Note 3)

Note

The Number shown within the box defines the arbitration phase where the particular bit may change state

Note 1

Note that the STATE Register is updated in each Phase of Arbitration

Note 2

This is the new Masters Competition Number

Note 3

Parking is only a Phase 0 event

Note

‘‘X’’ means that any Phase can update this bit (or bits)

Note

‘‘’’ is used in the table to depict the condition where a particular Status bit is Reset and where it is Set (Ex 0 1 means that this Status bit is Reset in Phase 0

and Set in Phase 1)

Note

‘‘-‘‘ is used in the table to depict the condition where a particular Status bit may change within several sequential phases (Ex 2-4 means that this Status bit

can change in Phases 2 3 or 4)

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