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DS3875 Datasheet(PDF) 24 Page - National Semiconductor (TI) |
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DS3875 Datasheet(HTML) 24 Page - National Semiconductor (TI) |
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24 / 58 page ![]() 50 Arbitrating for Futurebusa (Continued) TLH10747 – 17 FIGURE 7b Phase 1 Arbitration State Diagram Note 1 Idle Bus Arbitration during Phase 1 is not an internal state of the Arbitration Controller It is shown in this state diagram only to give a better understanding of Phase 1 arbitration Note 2 One bit on the parallel data bus is driven by external logic (the arbitration controller only drives the IBA CMPT output) only if IBA is supported by the module Note that the arbitration controller does not require AS DS DI external logic will require these conditions (from the Futurebusa specification) Note 3 If a module does not want IBA to select a new master external logic around the arbitration controller will drive di This transition is shown in this diagram to allow a clearer understanding of how IBA relates to normal arbitration Note 4 Competing e ‘‘ BRQ a MGRQ a Dummy Cycle’’ W e W bit of STATUS register Note 5 These Requests must have occurred before APO was asserted or they will not compete until the next arbitration cycle Note 6 The possible metastable condition of ‘‘( BRQ a MGRQ a Dummy Cycle) occurring at the same time as API’’ must be resolved before driving ARO Note 7 All conditions shown above the Phase 1 state must be completed before driving ARO 24 |
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