DS3875 datasheet(20/58 Pages) NSC

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50 Arbitrating for Futurebusa (Continued)

C Multiple Accesses AS

CANCEL Timing Diagram (AS is latched before being input to the AS

CANCEL

input of the Arbitration Controller At the end of the last transfer the latch is reset)

TLH10747 – 14

D Multiple Accesses AS

CANCEL Timig Diagram (AS is tied directly to the AS

CANCEL input

of the Arbitration Controller The Master must guarantee that the second transfer or ENDT

will come within

1 ms of the falling edge of the initial transfer AS signal)

TLH10747 – 15

FIGURES 6c 6d Timing of the AS

CANCEL Signal

551 Phase 0 Idle Phase

This Phase is characterized by AP released and AR as-

serted on Futurebusa and AQf negated on the module

board See

Figure 7a for the DS3875 Arbitration Controller

Phase 0 state diagram

The arbitration controller will be negating APO asserting

ARO and be receiving AQI negated This is the state of the

arbitration synchronization lines when no control acquisition

cycle is in progress or between the two control acquisition

cycles of a two-pass arbitration sequence

While in Phase 0 the following actions are performed

1 If

HALT is asserted the arbitration controller will not

transition to Phase 1 until HALT is negated

2 If any of the ‘‘New Bits’’ are set (NCN NGO NDS) the

corresponding internal arbitration controller registers will

be updated and then the ‘‘New Bits’’ will be reset

3 The arbitration condition lines (AC1

AC0 ) will be nega-

ted

One of the following three types of arbitration may occur

during Phase 0

1 Normal arbitration

2 Idle Bus Arbitration (IBA)

3 Parking

5511 Phase 0 Normal Arbitration Events That Cause a

Transition to Phase 1

There are five conditions during normal arbitration where

APO will be asserted causing a transition to Phase 1

1 If Two-Pass Arbitration is selected a bus request has

been received ( BRQ

MGRQ

Dummy Cycle)

and this module was a winner during the first pass of

arbitration then APO will be asserted

2 Though this module may not be requesting Futurebusa

another module may want to arbitrate for Futurebusa

and assert AP

This action will cause the AP input (API)

on this module to be asserted API asserted will cause

this modules arbitration controller to assert APO

3 If this module is currently the master and LK is assert-

ed BGRNT is negated

ENDT has been received no

other requests have been received and API is negated

the module will initiate a dummy cycle to unlock its re-

sources by asserting APO (if it is doing Single Pass or the

First Pass of Two-Pass Arbitration)

4 A message request ( MGRQ ) will cause APO to be as-

serted (if it is doing Single Pass or the First Pass of Two-

Pass Arbitration)

Note that if both a bus request

( BRQ ) and

MGRQ

are received during phase 0

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