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10 Introduction to Futurebusa

Futurebusa is a high-performance asynchronous multi-

plexed addressdata backplane bus designed by the IEEE

8961 committee for use in a wide variety of multiprocessor

architectures The Futurebusa standard is a next genera-

tion backplane bus standard developed to a set of require-

ments including openness performance and system facili-

ties and flexibilities so as not to hinder systems using this

bus for many generations of computer systems Future-

busa is a single cache coherent backplane architecture

featuring scalability technology independent protocols and

explicit provisions to extend to future applications Require-

ments set for the Futurebusa architecture by the IEEE

8961 Futurebusa Working Group include

1 Architecture processor and technology independent

2 A basic asynchronous (compelled) transfer protocol

3 An optional extended source-synchronized protocol

4 No technology-based upper limit to bus performance

5 Fully distributed parallel and arbitration protocols

6 Support for fault-tolerant and high-availability systems

7 Support for cache-based shared memory

8 Compatible message transport definition

Compatibility of varying speed and technology boards con-

nected to the same Futurebusa backplane is dependent

upon broadcast capability or a snooping cache coherence

scheme The performance of a Futurebusa backplane is

scalable over time to allow a low-end 32-bit system operat-

ing at 100 Mbytessec to be expanded to a 256-bit system

operating at 32 Gbytessec in the future This performance

is attainable by the use of source-synchronized protocols

which eliminate spatial skews and receivers which are trig-

gered by the incident wave from the driver The synchroni-

zation protocol of the Futurebusa backplane allows the

synchronization domain of the sender to extend along the

backplane presenting only one synchronization interface

between the bus and the receiver

The Futurebusa backplane uses ‘‘Backplane Transceiver

Logic’’ (BTL) BTL is a signaling standard that has been

developed to enhance the performance of backplane bus-

es This standard eliminates the settling time delays that

severely limit the TTL bus performance to provide signifi-

cantly higher bus transfer rates BTL compatible transceiv-

ers feature low output capacitance drivers to minimize bus

loading a 1V nominal signal swing for reduced power con-

sumption and receivers with precision thresholds for maxi-

mum noise immunity For example all Futurebusa signals

are open collector with termination resistors (selected to

match the bus impedance) connected to 2V at both ends

The low voltage is typically 1V All Futurebusa signals are

active low indicated by an

after the signal name (Refer to

Table I) Further signals can be driven simultaneously by

several modules This requires that glitch filtering will be

needed for those times to filter out the transmission line

effect called the wire-or glitch Refer to the Futurebusa

specifications for details

TABLE I Signal Definitions

Signal Type

Terminology

Logic

TTL

BTL

Example Signal

Level

Active High

Asserted

Logic 1

Signal

Name

Negated

Logic 0

Active Low

Asserted

Logic 1

Signal

Name

Negated

Logic 0

Released

Logic 0

(Open Collector)

20 Introduction to Futurebusa

Arbitration

Futurebusa uses an evolved version of the Parallel Con-

tention Arbiter (see

Figure 4 ) Through the application of a

unique arbitration vector to this logic only one contender

will be uniquely selected as the winner This implementation

requires no central logic on the backplane and gains the

following advantages

1 The current master can see any requests and their priori-

ty to determine whether it should give up the bus

2 Multiple priority levels can be implemented to allow sys-

tems to allocate bus bandwidth to modules running the

most critical tasks

3 A Round Robin (fairness) protocol is implemented within

each priority level to ensure fair and equitable allocation

of bus tenure to all modules

4 A master elect can be preempted by a higher-priority con-

tender This allows the higher priority contender to ac-

cess the bus with minimum latency (with some sacrifice

to the system performance)

5 Arbitration Messages or events can be broadcast on the

arbitration bus without disturbing the current transaction

on the parallel bus Important system control functions

and interrupts can be sent using this mechanism without

the need of dedicated bus lines

6 A Module may support either Idle Bus Arbitration or Park-

ing Idle Bus Arbitration can be enabled by the current

master to decrease the arbitration latency when ony one

competitor is requesting the bus If Idle Bus Arbitration is

not selected then Parking may be enabled by the master

Parking allows the current master to regain bus tenure

(during Phase 0) to perform new bus transactions

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