DS3875 datasheet(14/58 Pages) NSC

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50 Arbitrating for Futurebusa (Continued)

521 Priority Field (PR)

The priority field represents a module’s priority class which

is determined by the system designer In the unrestricted

mode the length of this field is a maximum of eight bits

while in the restricted mode it is two bits

522 Round Robin Field (RR)

This field is represented by a single bit CN5 in both modes

of operation The round robin protocol ensures that all mod-

ules in the same priority class have fair and equal access of

the bus A module is allowed to get tenure of the bus in a

sequence defined by its value in the unique field

The round robin bit is adjusted by the Arbitration Controller

each time a transfer of tenure occurs in the module’s same

priority class whether or not the module is competing in the

control acquisition cycle In the module’s same priority

class the round robin bit is set when tenure of the bus is

transferred to a module with a larger unique field value or

the round robin bit is cleared when tenure of the bus is

transferred to a module with a lesser unique field value

In the event where the module’s arbitration number is

changed after the next control acquisition cycle the round

robin bit is adjusted accordingly

523 Unique Field (U)

The five bit unique field CN(4

0) guarantees the unique-

ness of the module’s arbitration number The unique num-

ber may correspond to the module’s geographical address

or may be allocated by the system designer as he chooses

while also in such a way that minimizes the arbitration set-

tling time The value ‘‘11111’’ is not allowed in systems us-

ing arbitration messages

53 ARBITRATION CATEGORIES

A module can be in one of six categories when a control

acquisition cycle is in progress

Competitor for the Parallel bus

Competitor to send a message

By-Stander

By-Stander who decides to invoke Pre-emption

Master

Master Elect

531 Competitor for the Parallel Bus

A Module may become a competitor for the parallel bus if it

issues a Bus Request ( BRQ ) to the arbitration controller

before the arbitration cycle Phase 1 starts see

Figure 5a

If the module issues a bus request and the arbitration cycle

is in phase 0 the controller will assert APO to start an arbi-

tration competition If an arbitration competition has already

started and the module’s bus request comes prior to API

being asserted on the arbitration bus the module may enter

this arbitration cycle If an arbitration competition has al-

ready started and the module’s bus request comes after

AP being asserted on the arbitration bus the module will

have to wait until the next arbitration cycle to compete (or

pre-empt the current arbitration cycle in Phase 3)

TABLE II Arbitration Number

Bit

CN7

CN6

CN5

CN4

CN3

CN2

CN1

CN0

Unrestricted ModeSingle Pass

Pass 1

PR0

Unrestricted ModeTwo Pass

Pass 1

PR7

PR6

PR5

PR4

PR3

PR2

PR1

Pass 2

PR0

Restricted Mode

Pass 1

PR1

PR0

Arbitration Message

Pass 1

11111111

Pass 2

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