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DS3875 Datasheet(PDF) 45 Page - National Semiconductor (TI) |
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DS3875 Datasheet(HTML) 45 Page - National Semiconductor (TI) |
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45 / 58 page  150 AC Parameters (Continued) AC Timing Parameters Unless otherwise stated TA e 0 Cto a70 C VCC e 5V g10% (Continued) All transitions are specified after the input signals are stable and valid for evaluation This table will describe the parameters as given in the following pages All values are given in nanoseconds (ns) unless otherwise stated Number Symbol Parameter Description Min Typ Max t401 tAC1IAR AC1I Asserted to ARO Asserted 12 21 t403 tCANAC1 AS Cancel Asserted to AC1O Asserted 7 19 t405 tARIO ARI Asserted to ARO Asserted 14 19 t407 tEDAR ENDT Asserted to ARO Asserted 15 25 t500 tARBG ARO Asserted to BGRNT Asserted 7 12 t501 tOAQ BGRNT MGTX UNLK or any Interrupt Asserted to AQO Negated 5 7 t502 tARFTR ARO Asserted to FSTR Negated 5 8 t503 tARIBC ARO Asserted to IBA CMPT Negated 5 8 t504 tARABSA ARO Asserted to MGTX UNLK or any Interrupt Asserted 5 9 tA1 tRSTPW RST Pulse Width 50 50 tA2 tRSTRE Output Reset Time 30 45 tA3 tRSTAR RST Negated to ARO Asserted 15 25 tA4 tRINTPW RINT Pulse Width 50 50 tA5 tRINTRE Output Initialization Reset Time 30 45 tB1 tCSPW CS Pulse Width 35 tB2 tCSPWN CS Recovery Time 15 tB3 tCSDKA CS Asserted to DSACK Asserted 12 18 tB4 tADDS ADD (30) Setup Time 52 tB5 tADDH ADD (30) Hold Time 65 tB6 tCSDKN CS Negated to DSACK Negated 7 12 tB7 tRWS R W Setup Time 0 tB8 tSELS SEL Setup Time 0 tB10 tDATASDK Data (70) Setup Time with Respect to DSACK 24 15 tB11 tDATAHDK Data (70) Hold Time with Respect to DSACK 00 tB12 tSELH SEL Hold Time 3 tB24 tDATASCS Data (70) Setup Time with Respect to CS Negated 15 6 tB25 tDATAHCS Data (70) Hold Time with Respect to CS Negated 5 5 tB27 tDATALZ Data (70) Low Z Time 14 22 tB28 tDATAV Data (70) Valid Time before DSACK tB29 tDATAA Data (70) Access Time with Respect to CS Asserted 22 30 tB30 tDATAHRC Data (70) Hold Time 610 tB31 tDATAHZ Data (70) Hi – Z Time 12 25 tC2 tABRDCNZ AB RE Negated to CN (70) TRI-STATE 0 0 tD1 tCSXINTN CS Asserted to any Interrupt Negated 22 36 tE1 tFSTR FSTR Recovery Time 80 45 |
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