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DS3875 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DS3875 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 58 page  TLH10747 November 1995 DS3875 Futurebusa Arbitration Controller General Description The DS3875 Futurebusa Arbitration Controller is a member of National Semiconductor’s Futurebusa chip set designed specifically for the IEEE 8961 Futurebusa standard The DS3875 implements Distributed Arbitration and Distributed Arbitration messages in a single chip The DS3875 interfaces with Futurebusa through the DS3885 BTL Arbitration Transceiver and the DS3884A BTL Handshake Transceiver The DS3885 BTL Arbitration Transceiver incorporates the competition logic needed for the Arbitration Number signal lines The DS3884A BTL Handshake Transceiver has selectable Wired-OR receiver glitch filtering The DS3884A is used for the Arbitration Se- quencing and Arbitration Condition signal lines Additional transceivers included in the Futurebusa chip set are the DS3883A BTL 9-bit Data Transceiver and the DS3886A BTL 9-bit Latching Data Transceiver The DS3886A transceiver features edge-triggered latches in the driver which may be bypassed during a fall-through mode and a transparent latch in the receiver The DS3883A trans- ceiver has no latches in either direction The Logical Interface Futurebusa Engine (LIFE) IO Proto- col Controller with 64-bit Data Path incorporates the Com- pelled Mode Futurebusa Parallel Protocol The Protocol Controller handles all the handshaking signals between the Futurebusa and the local bus interfaces and incorporates a DMA Controller with built-in FIFOs for fast queueing Features Y The controller implements the complete requirements of the IEEE 8961 specification as a subset of its fea- tures Y Supports Arbitration message sending and receiving Y Supports the two modes of operation (RESTRICTED UNRESTRICTED) Y Software configurable doublesingle pass operation slowfast IBAParking and restrictedunrestricted modes of arbitration Y Built-in 1 ms timer for use in the arbitration cycle Y User programmable 16 arbitration delays (8 slow and 8 fast) Y Built-in PLL for accurate delays The PLL accepts clocks from 2 MHz to 40 MHz in steps of 1 MHz Y Signal to unlock slave modules on transfer of tenure Auto unlock through a dummy cycle if the current mas- ter locked resources Y Programmable delay for releasing ar after issuing COMPETEIBA CMPT This is to ensure the assertion of the arbitration number during competition before the release of ar Also this delay ensures there is suffi- cient time to assert the ADDATA lines during Idle Bus Arbitration before the release of ar Y ReadWrite facility with data acknowledge for the host to load arbitration numbers an arbitration message and control registers Y On chip parity generator unloads the host of the addi- tional parity generation function Y Separate interrupts to indicate error occurrence and ar- bitration message received Interrupts cleared on a reg- ister write Error status is available in a separate status register Y A special output pin to indicate that a POWERFAIL message was received Y Hardwired register to hold the first word of the arbitra- tion message Y FIFO strobe provided to store more than one arbitration message externally to prevent overrun Y Idle Bus Arbitration (IBA) supported Y Parking implemented Y Bus initialization system reset and Live-insertion sup- ported (The logic to detect these conditions must be implemented externally) Y Testability in the form of reading from key registers which include the STATE MCW 1 ms timer and pro- grammable input clock divider TLH10747 – 1 National’s Futurebusa Chip Set Diagram C1995 National Semiconductor Corporation RRD-B30M115Printed in U S A |
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