This section describes the addressable registers and the ALL1s hardwired register

71 ALL1S

This register carries the first word of an arbitration message (h 1ff)

72 TXCN0

h 00

7

6

543210

0P7P6P5P4P3P2P1

Bit

Symbol

Description

0 – 6

P(17)

Priority field of the arbitration number

7

0

two pass arbitration

Note

The Parity bit CNp for the arbitration number is internally generated during the time the host writes the numbers into the controller The odd parity as

73 TXCN1

For the Unrestricted Mode this register stores the pass 2 arbitration number of a two pass arbitration or stores the single pass

7

6

5

4

3210

1P1

P0

RR

U4

U3

U2

U1

U0

Bit

Symbol

Description

0 – 4

U(04)

Uniqueness field of the arbitration number

5

RR

Round Robin bit of the arbitration number Note This bit is updated during phase 5 upon the

successful transfer of tenure See Table III

6

P0

Priority field of the arbitration number If configured as a two pass arbitor P0 is part of P(07) If

configured as a single pass arbitor P0 is the priority field If configured to arbitrate in restricted

mode then P0 is part of P(01)

7

1P1

This bit is fixed at one as specified in the spec for the pass 2 number of a two pass arbitration

and for the single pass arbitration number This bit is P1 for the restricted mode arbitration

number

Note

The Parity bit CNp for the arbitration number is internally generated during the time the host writes the numbers into the controller The odd parity as

34