DS3875 datasheet(40/58 Pages) NSC

40 / 58 page

90 ClockTimerDelay Lines (Continued)

TLH10747 – 24

FIGURE 9 PLL Timer and Test Circuitry

100 ResetInitializationPower Up

Two distinct input reset pins are available on the Arbitration

Controller RINT

(Bus Reset and Initialization) and RST

(Power Up Reset) These signals are activated by the mod-

ule upon detecting either RE (in an appropriate condition)

on Futurebusa or reset from the host or the Protocol Con-

troller Both these signals are asynchronous inputs so that

the reset function is performed immediately after the signal

is asserted

RINT may be asserted by external logic from RE being

asserted for at least 2 ms or some other appropriate condi-

tion When RINT is asserted ( RINT )

1 the arbitration controller is placed in phase 0

2 all outputs of the arbitration controller are negated ex-

cept ARO

3 The following registers are cleared RXCN0 RXCN1

RXMSG CLRERI CLRMGI CLRPFI andMCW bits of

the STATUS register

4 ST0 bit is set in the STATE register

5 Contents of other registers remain except for the round

robin (RR) bit of TXCN1 which is reset

The rising edge of RINT will release the arbiter from phase

0 This reset signal should be used during Futurebusa ini-

tialization

When RST is asserted ( RST )

1 all outputs of the arbitration controller are negated

2 the registers are set to default values as given in the

The rising edge of RST

will cause ARO to be asserted

causing the arbiter to be in phase 0 This reset signal should

be used during power-up and live withdrawal

Figure 10 illustrates how the reset and initialization signals

may be used during power up While powering up when

RINT is asserted for 100 ms – 200 ms the registers may be

programmed BRQ should not be issued until after 10 ms

after the register CTRL1 is programmed giving the PLL a

sufficient time to lock onto the CLK signal

DS3875 Datasheet(PDF) 40 Page - National Semiconductor (TI)