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DS3875 Datasheet(PDF) 41 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DS3875
Description  Futurebusa??Arbitration Controller
PDF  58 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DS3875 Datasheet(HTML) 41 Page - National Semiconductor (TI)

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100 ResetInitializationPower Up (Continued)
TLH10747 – 25
FIGURE 10a Programming Registers After Power-Up
TLH10747 – 26
FIGURE 10b Programming Registers During Bus Initialization
TLH10747 – 27
FIGURE 10c PLL Lock Period
110 Live Insertion
The arbitration Controller supports live insertion (see
Figure
11 ) When a module is being live inserted into an active
Futurebusa system it will be powered up and reset The
live inserted module will reset it’s arbitration controller with
the RST input and will drive re on the Futurebusa back-
plane
RE asserted will cause all active Futurebusa modules to
release their bus lines to prepare for live insertion to the
Futurebusa backplane
When all the active Futurebusa modules detect RE
as-
serted they should assert HALT to their arbitration control-
ler and limit the current parallel bus transaction to 128 ms
The active modules will then remain in Phase 0 upon com-
pletion of the current control acquisition cycle until HALT
is negated
When the live inserted module detects both
1 the Parallel bus in the Idle state (AS and AKf negated)
2 the arbitration bus lines in Phase 0
for 1 ms then it should assert ai (protocol controller) and
negate the RST input The arbitration controller will assert
ARO upon detecting the negation of RST
These actions
will complete the Futurebusa alignment The live inserted
module will then be in arbitration Phase 0 thus aligned with
the other live modules Then the live inserted module will
negate re
When the active modules detect the negation of RE they
negate the HALT input to their arbitration controllers thus
allowing arbitration competition to proceed
At this point the live inserted module can only participate as
a by-stander during the arbitration competition cycle until it
is programmed and 10 ms has elapsed (PLL lock on time)
Once the 10 ms has elapsed the module can enable arbitra-
tion competition by setting the GO bit in CTRL3 At this time
bus requests (BRQ
MGRQ ) can be accepted to join com-
petition for the parallel bus
41



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