DS3875 datasheet(22/58 Pages) NSC

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50 Arbitrating for Futurebusa (Continued)

There are seven conditions that will cause the arbitration

controller to negate APO

1 This module has had a Bus ReQuest ( BRQ ) won IBA

and asserted AC1O and AS

2 The current master releases AS ( AS

CANCEL) The

master has completed its transactions on the parallel

bus see

Figures 6b c d

3 This module detected the 1 ms timeout or a parity error

occurred during the arbitration cycle This error condition

will cause the assertion of AC0O and AC1O and ERINT

signals which will inhibit the transfer of tenure during this

arbitration cycle

4 Another module has detected that transfer of tenure is to

be inhibited (AC1I)

5 This module was competing and won the competition

where this is the first pass of a two pass arbitration cycle

6 This module did not compete (CMPT ) but now has a

bus request ( BRQ ) and its competition number is

greater than ( WIN

GT ) the modules competition

number that won the current arbitration competition This

module preempts the current arbitration competition by

asserting AC1O This inhibits the transfer of tenure dur-

ing this arbitration cycle and allows a new arbitration cy-

cle to be initiated in which this module can compete

7 This module was competing ( CMPT ) and won the com-

petition (W bit of Status register set) but the bus request

or message request has been negated (BRQ

MGRQ ) This error condition will cause the assertion of

AC0O AC1O and ERINT signals which will inhibit the

transfer of tenure during this arbitration cycle

After all the modules have negated AP

upon receiving

API the arbitration cycle will transition to Phase 4

5541 Phase 3 Idle Bus Arbitration Events That Cause

a Transition to Phase 4

During phase 3 of the arbitration cycle when the current

master has not yet released the bus (AS) the new master (a

module that was competing (IBA

CMPT ) and won

(IBA

S )) will drive AC1O to inhibit the transfer of tenure

during the normal bus arbitration cycle (tenure was trans-

ferred during the IBA cycle)

Note

The new master will now continue the normal arbitration process to

completion but may begin conducting transactions on the bus

555 Phase 4 Master Release Phase

This Phase is characterized by AP released AQ asserted

and AR released on Futurebusa See

Figure 7e for the

DS3875 Arbitration Controller Phase 4 state diagram and

Figures 6b c d for how AS

CANCEL relates to phase 4

The arbitration controller will be receiving API negated as-

serting AQO and negating ARO This is the state of the

arbitration synchronization lines when the master release

phase (4) is in progress

While in Phase 4 the following actions are performed

1 All modules other then the bus master start a 1 ms tim-

er This is referred to as the Master release timer The

master has 1 ms to complete its transactions or to inhibit

the transfer of tenure and proceed to phase 5 This timer

is specified in the Futurebusa specification so in the

event where the current master does not respond the

master elect may assume mastership during phase 5

2 The CMPT signal is negated (CMPT )

There are six conditions that can cause ARO to be asserted

causing a transition to Phase 5

1 Transfer of tenure is inhibited indicated by the assertion

of AC1I

2 Was not Master and the ARI input was asserted

3 Was Master and did not cancel ( AS

CANCEL) the ar-

bitration competition see

Figures 6b c d

4 There is no current master (immediately following power

up) so the master elect may assert ARO

5 Was Master and did cancel ( AS

CANCEL) the arbitra-

tion competition see

Figure 6d In this case the current

master will assert AC1O to inhibit the transfer of tenure

during this arbitration cycle

6 All modules other then the current master detect the

Master Release Timeout

556 Phase 5 Tenure Transfer Phase

This Phase is characterized by AP released AQ asserted

and AR

asserted on Futurebusa See

Figure 7f for the

DS3875 Arbitration Controller Phase 5 state diagram

The arbitration controller will be negating API and asserting

AQO and ARO This is the state of the arbitration synchroni-

zation lines when the tenure transfer phase (5) is in prog-

ress

While in Phase 5 the following actions are performed

1 If IBA

CMPT

signal was asserted it is now negated

(IBA

CMPT )

2 The unlock signal ( UNLK ) will be asserted if locked

( LKD ) is asserted and the arbitration condition signals

(AC0I AC1I) are negated

3 This phase will update the following status bits

1 The Master status bit (bit 5) in the status register

2 The Competitor status bit (bit 4) in the status register

3 The WIN status bit (bit 3) in the status register

4 The Uniqueness round robin and priority fields of the

RXCN1 register

5 The Priority field of the RXCN0 register

There are four conditions that can cause AQO to be negat-

1 Had a message request ( MGRQ ) and won the compe-

tition ( WIN

GT ) In this case the message transmit-

ted output will also be asserted ( MSGTX )

2 Competed for the bus ( CMPT ) there were no errors

( AC0I

AC1I) and won the competition ( WIN

GT )

In this case the bus grant output will be asserted

( BGRNT ) and the internal master bit will be set (M bit

5 in the status register)

3 There were no errors ( AC0I

AC1I) and the module is

not the winner Resets the M bit in the status register

4 A Message was received In this case either message

interrupt will be asserted ( MGINT ) or the powerfail in-

terrupt ( PFINT ) will be asserted

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