DS3875 datasheet(18/58 Pages) NSC

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50 Arbitrating for Futurebusa (Continued)

acquisition synchronization signals (AP

AR ) the

parallel bus address handshake signals (AS

AI ) the

parallel bus data sync signal (DS ) and data acknowledge

inverse (DI ) and the IBA

CPT output from the arbitration

controller

542 Parking

During Power Up the Arbitration Controller is programmed

to perform either Idle Bus Arbitration or Parking by setting or

clearing the IBAPK

bit in the CTLR3 register Parking is

selected by clearing the IBAPK bit The aim of Parking is to

give the Futurebusa bus Master quick access to the bus to

perform other transfers when no one else desires to use it

Thus it is not necessary for the master to go through the

entire arbitration cycle to get the BGNT signal Parking is-

sues BGNT in Phase 0 see

Figure 5c If another module

gets a message request or bus request the arbitration com-

petition cycle begins like it normally does to handle the re-

quest

All of the following conditions should be met to take advan-

tage of Parking

1 Parking in selected

2 module must be the current Master

3 ENDT signal is high

4 BGRNT signal is high

5 BRQ signal is asserted low while in phase 0

6 LKD signal is high (Resources are not locked)

When these conditions are true the Arbitration Controller

issues the BGRNT signal (asserted low) in phase 0 Upon

end of tenure BGRNT signal will be released The Master

may continue to use Parking to perform transactions until

after the arbitration competition cycle selects a new master

(see

Figures 5c and 7 )

Parking is allowed only when the Master has all resources

unlocked (indicated by LKD

signal being high) During

phase 0 if the master still has resources locked (ENDT

and BGRNT signals are high) the Arbitration Controller will

immediately initiate a dummy cycle to unlock resources The

UNLK

signal is generated during phase 5 upon the suc-

cessful transfer of tenure The transfer of tenure may be

with itself or another module

55 THE ARBITRATION PHASES

The arbitration process consists of transitioning through six

phases (Phase 0 thru Phase 5) of the three arbitration syn-

chronization signals (AP

AR ) To transition between

control acquisition phases only one of the three arbitration

synchronization signals will transition

The Arbitration process is asynchronous and occurs as fast

as all the modules that contain arbitration logic can tran-

sition through the arbitration phases If a two-pass arbitra-

tion competition has been selected the entire control acqui-

sition cycle is repeated twice

Each arbitration synchronization signal (AP

AR )

represents the wire-OR of each of the individual synchroni-

zation signals from each of the modules For any of the

synchronization signals on the bus to be released all the

modules must release their individual synchronization sig-

nals (ap

ar ) Therefore the release of a synchroniza-

tion signal forms a global synchronization point for all the

modules Likewise during the assertion of a synchronization

signal all modules must remain synchronized by asserting

their own signals in response

Each module must participate in the control acquisition cy-

cle whether or not the module is competing to remain syn-

chronized with the other modules

Figure 6 is a timing dia-

gram of the Control Acquisition Sequence

Figures 7a – f are

state transition diagrams of the DS3875 Arbitration Control-

ler Tables III and IV represent the internal register bits that

are affected by the arbitration states and their transitions

The DS3875 Arbitration Controller transitions to the next

arbitration phase upon (see

Figure 6 )

1 APO output signal being asserted to phase 1

2 ARI input signal being negated to phase 2 (This input is

filtered and indicates all modules have released the AR

synchronization signal on the Futurebusa backplane)

3 AQO output signal being asserted to phase 3

4 API input signal being negated to phase 4 (This input is

filtered and indicates all modules have released the AP

synchronization signal on the Futurebusa backplane)

5 ARO output signal being asserted to phase 5

6 AQI input signal being negated to phase 0 (This input is

filtered and indicates all modules have released the AQ

synchronization signal on the Futurebusa backplane)

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