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DS3875 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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DS3875 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 58 page ![]() 30 Introduction to DS3875 Arbitration Controller (Continued) only describes one method of operation This method com- pletely corresponds to the Unrestricted mode In the DS3875 the R-U bit in the CTRL2 register configures the operation mode of the arbiter On reset the arbiter is placed in the unrestricted mode in accordance to the 8961 specifi- cation Arbitration Competition Settling Time Distributed Arbitration uses contention logic to select the winner of the competition cycle The Arbitration competition begins with all competing modules asserting the most signif- icant bit AB 7 of the competition number onto the back- plane lines A bit wise comparison is performed where mod- ules are allowed to assert the subsequent bits only as long as that module’s competition number bits thus far asserted are greater than or equal to the bits seen on the backplane lines Thus all competing modules begin asserting their competition numbers onto the backplane lines but at the end only the winning module will be allowed to assert it’s competition number onto the backplane lines When the DS3875 was designed two speeds where al- lowed in the FBUSabackplane system for the arbitration competition settling time Slow or fast During the arbitration cycle modules would indicate if they had a fast or slow competition settling time If any module indicated that it had a slow competition settling time then all modules would compete using the slow competition settling time else the fast settling time would be used during the competition cy- cle The DS3875 allows the user to program a fast or a slow competition settling time One of eight settling times can be selected for each mode with 16 total possible delay times The IEEE 8961 specification now allows each module to use it’s worst case arbitration settling time tA as the mod- ule’s delay time to determine it’s winlose status for the arbitration competition The ones and zeros combination in the competition number plays a significant role in determin- ing the numbers settling time Several factors are incorpo- rated into the tA calculation tpd Maximum end to end signal propagation delay along the transmission line (backplane) This is a function of the maximum length of the transmission line tint Delay between a change on any arbitration line ABx on the input to a module and the correspond- ing change on that module’s adjacent arbitration output ab x-1 orabp as its competition number is applied to or withdrawn from those bits text Delay between a change on any arbitration line ABx onthe input of any other competing module and the corresponding changes on that module’s ar- bitration outputs ab x-1 orabp as its competi- tion number is applied to or withdrawn from those bits twin Maximum delay between the time when the arbitra- tion bus AB 70 becomes stable and equivalent to cn 70 on the input to a module and the indica- tion within that module that it is the winner (Refer to 8961 for more details) Thus now each module can evaluate it’s winlose condition when it’s tA time has elapsed During a particular competi- tion the winning module’s competition number will have the longest worst case settling time since this is the module that has placed all of it’s competition number bits onto the FBUSa To use the DS3875 in the 8961 compliant mode the user programs two delay values in the CTRL2 register that are closest to the calculated worst case settling time for the particular competition number The F S bit should corre- spond to the table (fast or slow) that the most desired delay resides The CTRL2 register bits PD3 to PD5 program the delay number that corresponds to the fast mode operation and PD0 to PD2 program the delay number that corre- sponds to the slow mode operation Thus a delay that is closest to the desired delay time should be selected both from the fast (PD3 to PD5) table and the slow (PD0 to PD2) table The F S bit will configure this arbiter in the fast or slow mode of operation 8 |
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