TMS320VC5502 datasheet(4/189 Pages) TI

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Contents

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

TMS320VC5502

................................................................................................................. 15

1.1

Features

..................................................................................................................... 15

Introduction

....................................................................................................................... 16

2.1

Description

.................................................................................................................. 16

2.2

Pin Assignments

............................................................................................................ 17

2.2.1

Ball Grid Array (GZZ and ZZZ)

................................................................................ 17

2.2.2

Low-Profile Quad Flatpack (PGF)

............................................................................. 19

2.2.3

Signal Descriptions

.............................................................................................. 21

Functional Overview

........................................................................................................... 33

3.1

Memory

...................................................................................................................... 34

3.1.1

On-Chip ROM

................................................................................................... 34

3.1.2

On-Chip Dual-Access RAM (DARAM)

........................................................................ 35

3.1.3

Instruction Cache

................................................................................................ 35

3.1.4

Memory Map

..................................................................................................... 36

3.1.5

Boot Configuration

............................................................................................... 37

3.2

Peripherals

.................................................................................................................. 37

3.3

Configurable External Ports and Signals

................................................................................ 38

3.3.1

Parallel Port Mux

................................................................................................ 38

3.3.2

Host Port Mux

.................................................................................................... 39

3.3.3

Serial Port 2 Mux

................................................................................................ 40

3.3.4

External Bus Selection Register (XBSR)

..................................................................... 41

3.4

Configuration Examples

................................................................................................... 43

3.5

Timers

........................................................................................................................ 44

3.5.1

Timer Interrupts

.................................................................................................. 45

3.5.2

Timer Pins

........................................................................................................ 46

3.5.3

Timer Signal Selection Register (TSSR)

..................................................................... 47

3.6

Universal Asynchronous Receiver/Transmitter (UART)

............................................................... 48

3.7

Inter-Integrated Circuit (I2C) Module

..................................................................................... 50

3.8

Host-Port Interface (HPI)

.................................................................................................. 51

3.9

Direct Memory Access (DMA) Controller

................................................................................ 52

3.9.1

DMA Channel 0 Control Register (DMA_CCR0)

........................................................... 52

3.10

System Clock Generator

.................................................................................................. 54

3.10.1

Input Clock Source

.............................................................................................. 55

3.10.2

Clock Groups

..................................................................................................... 57

3.10.3

EMIF Input Clock Selection

.................................................................................... 58

3.10.4

Changing the Clock Group Frequencies

..................................................................... 58

3.10.5

PLL Control Registers

.......................................................................................... 60

3.10.6

Reset Sequence

................................................................................................. 72

3.11

Idle Control

.................................................................................................................. 72

3.11.1

Clock Domains

................................................................................................... 73

3.11.2

IDLE Procedures

................................................................................................ 73

3.11.3

Module Behavior at Entering IDLE State

..................................................................... 75

3.11.4

Wake-Up Procedure

............................................................................................ 76

3.11.5

Auto-Wakeup/Idle Function for McBSP and DMA

........................................................... 78

3.11.6

Clock State of Multiplexed Modules

........................................................................... 78

Contents

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