TMS320VC5502 datasheet(24/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 2-4. Signal Descriptions (continued)

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

The C3 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO23 or external memory interface control signal

EMIF.ARDY. The function of the C3 pin is determined by the state of the GPIO6 pin

I/O/Z

during reset. The C3 pin is set to PGPIO23 if GPIO6 is low during reset. The C3 pin

is set to EMIF.ARDY if GPIO6 is high during reset. The function of the C3 pin will be

set once the device is taken out of reset (RESET pin transitions from a low to high

state).

F, G, H, J

Parallel general-purpose I/O. PGPIO23 is selected when GPIO6 is low during

PGPIO23

I/O/Z

reset. The PGPIO23 signal is configured as an input after reset.

EMIF data ready pin. EMIF.ARDY is selected when GPIO6 is high during reset.The

EMIF.ARDY signal indicates that an external device is ready for a bus transaction to

be completed. If the device is not ready (EMIF.ARDY is low), the processor extends

EMIF.ARDY

the memory access by one cycle and checks EMIF.ARDY again. An internal pullup

is included to disable this feature if not used. The internal pullup can be disabled

through the External Bus Control Register (XBCR).

The C4 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO24 or external memory interface control signal

EMIF.CE0. The function of the C4 pin is determined by the state of the GPIO6 pin

I/O/Z

during reset. The C4 pin is set to PGPIO24 if GPIO6 is low during reset. The C4 pin

is set to EMIF.CE0 if GPIO6 is high during reset. The function of the C4 pin will be

set once the device is taken out of reset (RESET pin transitions from a low to high

C, D, E, F,

state).

G, H, M

Parallel general-purpose I/O. PGPIO24 is selected when GPIO6 is low during

PGPIO24

I/O/Z

reset. The PGPIO24 signal is configured as an input after reset.

EMIF chip-select for memory space CE0. EMIF.CE0 is selected when GPIO6 is

EMIF.CE0

O/Z

high during reset. The EMIF.CE0 signal is in a high-impedance state during reset

and is set to output after reset with an output value of 1.

The C5 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO25 or external memory interface control signal

EMIF.CE1. The function of the C5 pin is determined by the state of the GPIO6 pin

I/O/Z

during reset. The C5 pin is set to PGPIO25 if GPIO6 is low during reset. The C5 pin

is set to EMIF.CE1 if GPIO6 is high during reset. The function of the C5 pin will be

set once the device is taken out of reset (RESET pin transitions from a low to high

C, D, E, F,

state).

G, H, M

Parallel general-purpose I/O. PGPIO25 is selected when GPIO6 is low during

PGPIO25

I/O/Z

reset. The PGPIO25 signal is configured as an input after reset.

EMIF chip-select for memory space CE1. EMIF.CE1 is selected when GPIO6 is

EMIF.CE1

O/Z

high during reset. The EMIF.CE1 signal is in a high-impedance state during reset

and is set to output after reset with an output value of 1.

The C6 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO26 or external memory interface control signal

EMIF.CE2. The function of the C6 pin is determined by the state of the GPIO6 pin

I/O/Z

during reset. The C6 pin is set to PGPIO26 if GPIO6 is low during reset. The C6 pin

is set to EMIF.CE2 if GPIO6 is high during reset. The function of the C6 pin will be

set once the device is taken out of reset (RESET pin transitions from a low to high

C, D, E, F,

state).

G, H, M

Parallel general-purpose I/O. PGPIO26 is selected when GPIO6 is low during

PGPIO26

I/O/Z

reset. The PGPIO26 signal is configured as an input after reset.

EMIF chip-select for memory space CE2. EMIF.CE2 is selected when GPIO6 is

EMIF.CE2

O/Z

high during reset. The EMIF.CE2 signal is in a high-impedance state during reset

and is set to output after reset with an output value of 1.

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