TMS320VC5502 datasheet(23/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 2-4. Signal Descriptions (continued)

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

Parallel Port — Control Pins

The C0 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO20 or external memory interface control signal

EMIF.ARE/SADS/SDCAS/SRE. The function of the C0 pin is determined by the

I/O/Z

state of the GPIO6 pin during reset. The C0 pin is set to PGPIO20 if GPIO6 is low

during reset. The C0 pin is set to EMIF.ARE/SADS/SDCAS/SRE if GPIO6 is high

during reset. The function of the C0 pin will be set once the device is taken out of

reset (RESET pin transitions from a low to high state).

Parallel general-purpose I/O. PGPIO20 is selected when GPIO6 is low during

PGPIO20

I/O/Z

C, D, E, F,

reset. The PGPIO20 signal is configured as an input after reset.

G, H, M

EMIF control pin. EMIF.ARE/SADS/SDCAS/SRE is selected when GPIO6 is high

during reset. The EMIF.ARE/SADS/SDCAS/SRE signal is in a high-impedance state

during reset and is set to output after reset with an output value of 1.

EMIF.ARE/SADS/

The EMIF.ARE/SADS/SDCAS/SRE signal serves four different functions when used

O/Z

SDCAS/SRE

by the EMIF: asynchronous memory read-enable (EMIF.ARE), synchronous memory

address strobe (EMIF.SADS), SDRAM column-address strobe (EMIF.SDCAS), and

synchronous read-enable (EMIF.SRE) (selected by RENEN in the CE Secondary

Control Register 1).

The C1 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO21 or external memory interface control signal

EMIF.AOE/SOE/SDRAS. The function of the C1 pin is determined by the state of

I/O/Z

the GPIO6 pin during reset. The C1 pin is set to PGPIO21 if GPIO6 is low during

reset. The C1 pin is set to EMIF.AOE/SOE/SDRAS if GPIO6 is high during reset.

The function of the C1 pin will be set once the device is taken out of reset (RESET

pin transitions from a low to high state).

C, D, E, F,

Parallel general-purpose I/O. PGPIO21 is selected when GPIO6 is low during

PGPIO21

I/O/Z

G, H, M

reset. The PGPIO21 signal is configured as an input after reset.

EMIF control pin. EMIF.AOE/SOE/SDRAS is selected when GPIO6 is high during

reset. The EMIF.AOE/SOE/SDRAS signal is in a high-impedance state during reset

EMIF.AOE/SOE/

and is set to output after reset with an output value of 1.

O/Z

SDRAS

The EMIF.AOE/SOE/SDRAS signal serves three different functions when used by

the EMIF: asynchronous memory output-enable (EMIF.AOE), synchronous memory

output-enable (EMIF.SOE), and SDRAM row-address strobe (EMIF.SDRAS).

The C2 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO22 or external memory interface control signal

EMIF.AWE/SWE/SDWE. The function of the C2 pin is determined by the state of the

I/O/Z

GPIO6 pin during reset. The C2 pin is set to PGPIO22 if GPIO6 is low during reset.

The C2 pin is set to EMIF.AWE/SWE/SDWE if GPIO6 is high during reset. The

function of the C2 pin will be set once the device is taken out of reset (RESET pin

transitions from a low to high state).

C, D, E, F,

Parallel general-purpose I/O. PGPIO22 is selected when GPIO6 is low during

PGPIO22

I/O/Z

G, H, M

reset. The PGPIO22 signal is configured as an input after reset.

EMIF control pin. EMIF.AWE/SWE/SDWE is selected when GPIO6 is high during

reset. The EMIF.AWE/SWE/SDWE signal is in a high-impedance state during reset

EMIF.AWE/SWE/

and is set to output after reset with an output value of 1.

O/Z

SDWE

The EMIF.AWE/SWE/SDWE signal serves three different functions when used by

the EMIF: asynchronous memory write-enable (EMIF.AWE), synchronous memory

write-enable (EMIF.SWE), and SDRAM write-enable (EMIF.SDWE).

Introduction

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