TMS320VC5502 datasheet(48/189 Pages) TI

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3.6

Universal Asynchronous Receiver/Transmitter (UART)

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 3-8. Timer Signal Selection Register Bit Field Description (continued)

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IWCON

2:1

R/W

Internal WDT output signal connection

•

IWCON = 00:

Internal watchdog timer interrupt (TINT) signal has no internal

connection.

•

IWCON = 01:

Internal watchdog timer interrupt (TINT) signal has an internal

connection to RESET pin.

•

IWCON = 10:

Internal watchdog timer interrupt (TINT) signal has an internal

connection to NMI pin.(1)

•

IWCON = 11:

Internal watchdog timer interrupt (TINT) signal has an internal

connection to INT3 pin.

NMI/WDTOUT_CFG

R/W

NMI/WDTOUT configuration

•

NMI/WDTOUT_CFG = 0:

NMI/WDTOUT pin is used as the WDTOUT pin.

•

NMI/WDTOUT_CFG = 1:

NMI/WDTOUT pin is used as the NMI input pin.(1)

(1)

If NMI/WDTOUT_CFG = 1 and IWCON = 10, only the WDTOUT signal will drive the NMI signal; the external source driving the

NMI/WDTOUT pin will be ignored.

The UART peripheral is based on the industry-standard TL16C550B asynchronous communications

element, which in turn, is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on

power up (character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550)

mode. This relieves the CPU of excessive software overhead by buffering received and transmitted

characters. The receiver and transmitter FIFOs store up to 16 bytes, including three additional bits of error

status per byte for the receiver FIFO.

The UART performs serial-to-parallel conversions on data received from a peripheral device or modem

and parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at

any time. The UART includes control capability and a processor interrupt system that can be configured to

minimize software management of the communications link.

The UART includes a programmable baud rate generator capable of dividing the CPU clock by divisors

from 1 to 65535 and producing a 16

× reference clock for the internal transmitter and receiver logic.

The UART pins are multiplexed with the pins of McBSP2. The Serial Port 2 Mux determines which pins

are connected to the SP0, SP1, SP2, and SP3. If GPIO7 is low at reset, the Serial Port 2 Mux Mode bit in

the External Bus Selection Register (XBSR) will be set to 0 to indicate that the UART module is enabled.

In this mode, the TX and RX signals of the UART will be routed to the SP1 and SP3 pins, respectively. If

GPIO7 is high at reset, the Serial Port 2 Mux Mode bit will be set to 1 to indicate that the UART module is

disabled. In this mode, any reads or writes to the UART registers will result in bus errors if the PERITOEN

bit of the Time-Out Control Register is set to 1.

Functional Overview

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