TMS320VC5502 datasheet(74/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.11.2.4

EMIF Module Idle Procedure

The 5502 EMIF can be idled in one of two ways: through the ICR and through the PICR. The EMIF will go

into idle immediately if there is no data transfer taking place within the DMA. If there is a data transfer

taking place, then the EMIF will wait until the DMA finishes the current transfer and goes into idle before

going into idle itself. Please note that while the EMIF is in idle, the SDRAM refresh function of the EMIF

will not be available.

The 5502 EMIF can be idled through the ICR only when the following modules are set to idle: CPU, I-Port,

ICACHE, DMA, and HPI. To place the EMIF in idle using the ICR, execute the following procedure:

1. Write '1' to the DMA and HPI bits in MICR.

2. Write '1' to the CPUI, MPI, ICACHEI, EMIFI, and IPORTI bits in ICR.

3. Execute the IDLE instruction.

4. EMIF and all modules listed in Step 2 will go to idle.

The 5502 EMIF can also be idled through the PICR. To place the EMIF in idle using the PICR, execute

the following procedure:

1. Write a '1' to the EMIF bit in PICR.

2. Write a '1' to the PERI bit in ICR.

3. Execute IDLE instruction.

4. EMIF will go to IDLE.

3.11.2.5

IDLE2 Mode

In IDLE2 mode, all modules except the CLOCK module are set to idle state. To place the 5502 in IDLE2

mode, perform the following steps.

1. Write a '1' to all peripheral module bits in the PICR.

2. Write a '1' to the HPI and DMA bits in MICR.

3. Write a '1' to all domain bits in the ICR except the CLOCK domain bit (CLKI).

4. Execute the IDLE instruction.

5. All internal clocks will be disabled, the CLOCK module will remain active.

3.11.2.6

IDLE3 Mode

In IDLE3 mode, all modules (including the CLOCK module) are set to idle state. To place the 5502 in

IDLE3 mode, perform the following steps.

1. Clear (i.e., set to '0') the PLLEN bit in PLLCSR to place the PLL in bypass mode.

2. Set the PLLPWRDN and PLLRST bits in PLLCSR to '1'.

3. Write a '1' to all peripheral module bits in PICR (write 0x3FFF to PICR).

4. Write a '1' to the HPI and DMA bits in MICR (write 0x0003 to MICR).

5. Write a '1' to all domain bits and bit 9 in the ICR (write 0x03FF to ICR).

6. Execute the IDLE instruction.

7. PLL core is set to power-down mode and all internal clocks are disabled.

3.11.2.7

IDLE3 Mode With Internal Oscillator Disabled

In this state, all modules (including the CLOCK module) are set to the idle state and the internal oscillator

is set to the power-down mode. This is the lowest power-consuming state that 5502 can be placed under.

1. Clear (i.e., set to '0') the PLLEN bit in PLLCSR to place the PLL in bypass mode.

2. Set the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR to '1'.

Functional Overview

TMS320VC5502 Datasheet(PDF) 74 Page - Texas Instruments

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