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TMS320VC5502 Datasheet(PDF) 82 Page - Texas Instruments |
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TMS320VC5502 Datasheet(HTML) 82 Page - Texas Instruments |
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82 / 189 page  www.ti.com TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004 Table 3-29. IDLE Status Register Bit Field Description (continued) BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION EMIFIS 5 R 0 External Memory Interface (EMIF) idle status bit • EMIFIS = 0: EMIF module is active • EMIFIS = 1: EMIF module is disabled CLKIS 4 R 0 Device clock generator idle status bit • CLKIS = 0: Device clock generator module is active • CLKIS = 1: Device clock generator is disabled PERIS 3 R 0 Peripheral idle status bit • PERIS = 0: All peripheral modules are active • PERIS = 1: All peripheral modules are disabled ICACHEIS 2 R 0 ICACHE idle status bit • ICACHEIS = 0: ICACHE module is active • ICACHEIS = 1: ICACHE module is disabled MPIS 1 R 0 DMA and HPI idle status bit • MPIS = 0: DMA and HPI modules are active • MPIS = 1: DMA and HPI modules are disabled CPUIS 0 R 0 CPU idle status bit • CPUIS = 0: CPU module is active • CPUIS = 1: CPU module is disabled 3.11.7.3 Peripheral IDLE Control Register (PICR) 15 14 13 12 11 10 9 8 Reserved MISC EMIF BIOST WDT PIO URT R, 00 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 7 6 5 4 3 2 1 0 I2C ID IO SP2 SP1 SP0 TIM1 TIM0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-28. Peripheral IDLE Control Register Layout (0x9400) 82 Functional Overview |
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