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3.11.5

Auto-Wakeup/Idle Function for McBSP and DMA

3.11.6

Clock State of Multiplexed Modules

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

To take the 5502 (including the internal oscillator) out of the idle 3 state, execute the following procedure:

1. External interrupt or NMI occurs (as specified in the WKEN register) and program flow begins after

41,032 reference clock cycles.

2. CPU wakes up.

3. Write '0' to all bits in the ICR.

4. Execute the IDLE instruction.

5. All internal clocks are enabled and all modules come out of idle.

6. Write '0' to the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR.

7. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.

8. Set the PLLEN bit in PLLCSR to '1'.

9. All internal clocks will now come from the PLL core.

NOTE

Step 2 can be modified to only wake up certain modules, see previous sections for more

information on the wake-up procedures for the 5502 modules.

3.11.4.8

Summary of Wake-up Procedures

Table 3-26 summarizes the wake-up procedures.

Table 3-26. Wake-Up Procedures

CLOCK DOMAIN

ISTR VALUE

EXIT FROM IDLE

ICR AFTER WAKE-UP

ISTR AFTER WAKE-UP

STATUS

xxx0xxx0

CPU - ON

DSP software modifies ICR 1.

Modified value

Updated

ICR

modified

Clock Generator - ON

and executes "IDLE" instruc-

value after "IDLE" instruction

All "0"

Other - ON/OFF

tion

All "0"

Reset

xxx0xxx1

CPU - OFF

Unmasked interrupt from ex- 1.

Not modified

CPUIS,

CLKIS,

and

Clock Generator - ON

ternal or on-chip module

EMIFIS/XPORTIS/IPORTIS

All "0"

Other - ON/OFF

are set to "0"

Reset

All "0"

xxx11111

CPU - OFF

Unmasked interrupt from ex- 1.

Not modified

CPUIS,

CLKIS,

and

Clock Generator - OFF

ternal

EMIFIS/XPORTIS/IPORTIS

All "0"

Other - OFF

are set to "0"

Reset

All "0"

The 5502 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when

the DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode

and the McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state

automatically if the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state

automatically after data transfer is complete. [The clock generator (PLL) should be active and the PLL

core should not be in power-down mode for the Auto-wakeup/Idle function to work.]

The clock to the McBSP2, UART, and EMIF modules is disabled automatically when these modules are

not selected through the External Bus Selection Register (XBSR). Note that any accesses to disabled

modules will result in a bus error.

Functional Overview

TMS320VC5502 Datasheet(PDF) 78 Page - Texas Instruments

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