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3.11.7

IDLE Control and Status Registers

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

The clock domains are controlled by the IDLE Configuration Register (ICR) that allows the user to place

different parts of the device in Idle mode. The IDLE Status Register (ISTR) reflects the portion of the

device that remains active. The peripheral domain is controlled by the Peripheral IDLE Control Register

(PICR). The Peripheral IDLE Status Register (PISTR) reflects the portion of the peripherals that are in the

IDLE state. The Master IDLE Control Register (MICR) is used to place the HPI and DMA in Idle mode.

The IDLE state of the HPI and DMA is reflected by the Master IDLE Status Register (MISR). The PLL

Control/Status Register (PLLCSR) is used to power down the PLL core when the IDLE instruction is

executed.

The settings in the ICR, PICR, and MICR take effect after the IDLE instruction is executed. For example,

writing xxx000001b into the ICR does not indicate that the CPU domain is in IDLE mode; rather, it

indicates that after the IDLE instruction, the CPU domain will be in IDLE mode. Procedures for placing

portions of the device in Idle mode and taking them out of Idle mode are described in Section 3.11.2 (IDLE

Procedures) and Section 3.11.4 (Wake-Up Procedures), respectively.

Table 3-27. Clock Domain Memory-Mapped Registers

ADDRESS

0x0001

IDLE Configuration Register (ICR)

0x0002

IDLE Status Register (ISTR)

0x9400

Peripheral IDLE Control Register (PICR)

0x9401

Peripheral IDLE Status Register (PISTR)

0x9402

Master IDLE Control Register (MICR)

0x9403

Master IDLE Status Register (MISR)

3.11.7.1

IDLE Configuration Register (ICR)

Reserved

CLKEI(1)

IPORTI

R, 000000

R/W, 0

MPORTI

XPORTI

EMIFI

CLKI

PERI

ICACHEI

MPI

CPUI

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

(1)

This bit must be set to '1' when placing the clock generator in idle; otherwise, a bus error interrupt will be generated.

Figure 3-26. IDLE Configuration Register Layout (0x0001)

Functional Overview

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