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TMS320VC5502 Datasheet(PDF) 49 Page - Texas Instruments |
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TMS320VC5502 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 189 page  www.ti.com 8 Receiver Buffer Register Divisor Latch (LS) Divisor Latch (MS) Baud Generator Receiver FIFO Line Status Register Transmitter Holding Register Modem Control Register Line Control Register Transmitter FIFO Interrupt Enable Register Interrupt Identification Register FIFO Control Register Interrupt/ Event Control Logic S e l e c t Data Bus Buffer RX TX Peripheral Bus S e l e c t Receiver Shift Register Receiver Timing and Control Transmitter Timing and Control Transmitter Shift Register Control Logic 16 8 8 8 8 8 Interrupt to CPU 16 8 signal signal 8 8 8 8 Power and Emulation Control Register Event to DMA controller TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004 Figure 3-9. UART Functional Block Diagram Functional Overview 49 |
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