TMS320VC5502 datasheet(30/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 2-4. Signal Descriptions (continued)

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

Oscillator/Clock Pins

Clock output. CLKOUT can be set to reflect the clock of the Fast Peripherals Clock

Group, Slow Peripherals Clock Group, and the External Memory Interface Clock

Group. The CLKOUT pin is set to the internal clock SYSCLK1 during and after reset.

CLKOUT

O/Z

SYSCLK1 is set equal to a divided-by-four CLKIN or OSCOUT (depending on the

state of the GPIO4 pin) during and after reset. SYSCLK1 is used to clock the Fast

Peripheral Clock Group.

Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN

X2/CLKIN

functions as the clock input.

Output pin from the internal oscillator for the crystal. If the internal oscillator is

not used, X1 should be left unconnected.

Multichannel Buffered Serial Port Pins (McBSP0 and McBSP1)

C, F, G, H, Receive clock input of McBSP0. The CLKR0 pin is configured as an input after

CLKR0

I/O/Z

reset.

DR0

L, G

Serial data receive input of McBSP0

Frame synchronization pulse for receive input of McBSP0. The FSR0 pin is

FSR0

I/O/Z

F, G, H, M

configured as an input after reset.

C, F, G, H,

CLKX0

I/O/Z

Transmit clock of McBSP0. The CLKX0 pin is configured as an input after reset.

Serial data transmit output of McBSP0. The DX0 pin is in a high-impedance state

DX0

O/Z

F, H, M

during and after reset.

Frame synchronization pulse for transmit output of McBSP0. The FSX0 pin is

FSX0

I/O/Z

F, G, H, M

configured as an input after reset.

Receive clock input of McBSP1. The CLKR1 pin is configured as an input after

CLKR1

I/O/Z

C, G, H, M

reset.

DR1

L, G

Serial data receive input of McBSP1

Frame synchronization pulse for receive input of McBSP1. The FSR1 pin is

FSR1

I/O/Z

F, G, H, M

configured as an input after reset.

Serial data transmit output of McBSP1. The DX1 pin is in a high-impedance state

DX1

O/Z

F, H, M

during and after reset.

C, F, G, H,

CLKX1

I/O/Z

Transmit clock of McBSP1. The CLKX1 pin is configured as an input after reset.

Frame synchronization pulse for transmit output of McBSP1. The FSX1 pin is

FSX1

I/O/Z

F, G, H, M

configured as an input after reset.

Serial Port 2 (McBSP2/UART) Pins

DR2

L, G

McBSP2 data receive input

McBSP2 data transmit output. The DX2 pin is in a high-impedance state during

DX2

O/Z

F, H, M

and after reset.

The SP0 pin of Serial Port 2 serves one of two functions: GPIO3 or CLKX2. The

function of the SP0 pin is determined by the state of the GPIO7 pin during reset.

SP0

I/O/Z

C, F, M

The SP0 pin is set to GPIO3 if GPIO7 is low during reset. The SP0 pin is set to

CLKX2 if GPIO7 is high during reset. The function of the SP0 pin will be set once

the device is taken out of reset (RESET pin transitions from a low to high state).

GPIO3. GPIO3 is selected if GPIO7 is low during reset. The GPIO3 signal is

GPIO3

I/O/Z

G, H

configured as input after reset.

McBSP2 transmit clock. CLKX2 is selected if GPIO7 is high during reset. The

CLKX2

I/O/Z

G, H

CLKX2 signal is configured as input after reset.

The SP1 pin of Serial Port 2 serves one of two functions: UART.TX or CLKR2. The

function of the SP1 pin is determined by the state of the GPIO7 pin during reset.

SP1

I/O/Z

C, F, M

The SP1 pin is set to UART.TX if GPIO7 is low during reset. The SP1 pin is set to

CLKR2 if GPIO7 is high during reset. The function of the SP1 pin will be set once

the device is taken out of reset (RESET pin transitions from a low to high state).

UART transmit data output. UART.TX is selected if GPIO7 is low during reset. The

UART.TX

UART.TX signal outputs a value of 1 during and after reset.

McBSP2 receive clock. CLKR2 is selected if GPIO7 is high during reset. The

CLKR2

I/O/Z

G, H

CLKR2 signal is configured as input after reset.

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