TMS320VC5502 datasheet(97/189 Pages) TI

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3.13.1

External Bus Control Register (XBCR)

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Reserved

R, 00000000

EMU

TEST

WDT

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-43. External Bus Control Register Layout (0x8800)

Table 3-47. External Bus Control Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15-8

00000000

Reserved

EMU

R/W

EMU bit

•

EMU = 0: Pullups on EMU1 and EMU0 pins are enabled.

•

EMU = 1: Pullups on EMU1 and EMU0 pins are disabled.

TEST

R/W

TEST bit

•

TEST = 0: Pullups/pulldowns on test pins are enabled (does not

include EMU1 and EMU0 pins)

•

TEST = 1: Pullups/pulldowns on test pins are disabled (does not

include EMU1 and EMU0 pins)

WDT

R/W

WDT bit

•

WDT = 0: Pullup on NMI/WDTOUT pin is enabled

•

WDT = 1: Pullup on NMI/WDTOUT pin is disabled

R/W

HPI control signal bit

•

HC = 0: Pullups/pulldowns on HPI control pins (HC0 and HC1) are

enabled

•

HC = 1: Pullups/pulldowns on HPI control pins (HC0 and HC1) are

disabled

R/W

HPI data bus bit

•

HD = 0: Bus holders on HPI data bus (pins HD[7:0]) are enabled

•

HD = 1: Bus holders on HPI data bus (pins HD[7:0]) are disabled

R/W

EMIF control signals

•

PC = 0: Bus holders and pullups on EMIF control pins are enabled

•

PC = 1: Bus holders and pullups on EMIF control pins are disabled

R/W

EMIF data bus signals

•

PD = 0: Bus holders on EMIF data bus (pins D[31:0]) are enabled

•

PD = 1: Bus holders on EMIF data bus (pins D[31:0]) are disabled

R/W

EMIF address bus signals

•

PA = 0: Bus holders on EMIF address bus (pins A[21:2]) are

enabled

•

PA = 1: Bus holders on EMIF address bus (pins A[21:2]) are

disabled

Functional Overview

TMS320VC5502 Datasheet(PDF) 97 Page - Texas Instruments

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