TMS320VC5502 datasheet(91/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.12.2.3

Parallel GPIO Data Register 0 (PGPIODAT0)

IO15DAT

IO14DAT

IO13DAT

IO12DAT

IO11DAT

IO10DAT

IO9DAT

IO8DAT

R/W, pin

IO7DAT

IO6DAT

IO5DAT

IO4DAT

IO3DAT

IO2DAT

IO1DAT

IO0DAT

R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 3-36. Parallel GPIO Data Register 0 Layout (0x4402)

Table 3-39. Parallel GPIO Data Register 0 Bit Field Description

(1)

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IOxDAT

15-0

R/W

Depends on the signal level on

Data bits that are used to control the level of the

the corresponding I/O pin

corresponding I/O pins configured as output pins and to

monitor the level of the corresponding I/O pins configured

as input pins. See Table 3-36, TMS320VC5502 PGPIO

Cross-Reference.

If IOxDIR = 0, then:

•

IOxDAT = 0: Corresponding I/O pin is read as a low

•

IOxDAT = 1: Corresponding I/O pin is read as a high

If IOxDIR = 1, then:

•

IOxDAT = 0: Set corresponding I/O pin to low

•

IOxDAT = 1: Set corresponding I/O pin to high

(1)

x = value from 0 to 15

Functional Overview

TMS320VC5502 Datasheet(PDF) 91 Page - Texas Instruments

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