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2.2.3

Signal Descriptions

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 2-4 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2, Pin

Assignments, for exact pin locations based on package type.

Table 2-4. Signal Descriptions

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

Parallel Port — Address Bus

The A[21:18] pins of the Parallel Port serve one of two functions: parallel

general-purpose input/output (PGPIO) signals PGPIO[3:0] or external memory

interface (EMIF) address bus signals EMIF.A[21:18]. The function of the A[21:18]

pins is determined by the state of the GPIO6 pin during reset. The A[21:18] pins are

set to PGPIO[3:0] if GPIO6 is low during reset. The A[21:18] pins are set to

EMIF.A[21:18] if GPIO6 is high during reset. The function of the A[21:18] pins will be

set once the device is taken out of reset (RESET pin transitions from a low to high

A[21:18]

I/O/Z

state).

The A[21:18] bus includes bus holders to reduce the static power dissipation caused

C, D, E, F, by floating, unused pins. The bus holders also eliminate the need for external bias

G, H, M

resistors on unused pins. When the bus goes into a high-impedance state, the bus

holders keep the address bus at the logic level that was most recently driven. The

bus holders are enabled at reset and can be enabled/disabled through the External

Bus Control Register (XBCR).

Parallel general-purpose I/O. PGPIO[3:0] is selected if GPIO6 is low during reset.

PGPIO[3:0]

I/O/Z

The PGPIO[3:0] signals are configured as inputs after reset.

EMIF address bus. EMIF.A[21:18] is selected if GPIO6 is high during reset. The

EMIF.A[21:18]

O/Z

EMIF.A[21:18] signals are in a high-impedance state during reset and are configured

as outputs after reset with an output value of 0.

(1)

I = Input, O = Output, S = Supply, Z = High impedance

(2)

Other Pin Characteristics:

A - Internal pullup [always enabled]

B - Internal pulldown [always enabled]

C - Hysteresis input

D - Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E - Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If

EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F - Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G - Pin can be configured as a general-purpose input.

H - Pin can be configured as a general-purpose output.

J - Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K - Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

L - Fail-safe pin

M - Pin is in high-impedance during reset (RESET pin is low)

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