TMS320VC5502 datasheet(65/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.10.5.4

PLL Divider1 Register (PLLDIV1) for SYSCLK1

This register controls the value of the divider D1 for SYSCLK1. It is in both the BYPASS and PLL paths.

D1EN

Reserved

R/W, 1

R, 0000000

Reserved

PLLDIV1

R, 000

R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-18. PLL Divider 1 Register Layout (0x1C8C)

Table 3-16. PLL Divider 1 Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

D1EN

R/W

Divider D1 enable

•

D1EN = 0: Divider 1 disabled

•

D1EN = 1: Divider 1 enabled

Reserved

14:5

0000000000

Reserved. Reads return 0. Writes have no effect.

PLLDIV1

4:0

R/W

00011

Divider D1 ratio (SYSCLK1 divider)

•

PLLDIV1 = 00000: Divide by 1

•

PLLDIV1 = 00001: Divide by 2

•

PLLDIV1 = 00010: Reserved

•

PLLDIV1 = 00011: Divide by 4

•

PLLDIV1 = 00100–11111: Reserved

Functional Overview

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