TMS320VC5502 datasheet(29/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 2-4. Signal Descriptions (continued)

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

Non-maskable external interrupt or Watchdog Timer output.The function of this

pin is controlled by the Timer Signal Selection Register (TSSR). By default, the

NMI/WDTOUT pin has the function of the NMI signal.

NMI/WDTOUT

I/O/Z

C, F, J, M

NMI is an external interrupt that cannot be masked by the Interrupt Enable Registers

(IER0 and IER1). When NMI is activated, the interrupt is always performed.

WDTOUT serves as an input and output pin for the Watchdog Timer.

Interrupt acknowledge. IACK indicates the receipt of an interrupt and that the

IACK

O/Z

F, M

program counter is fetching the interrupt vector location designated on the address

bus. The IACK pin is set to a value of '1' during reset.

Device reset. RESET causes the digital signal processor (DSP) to terminate current

program execution. When RESET is brought to a high level, program execution

RESET

C, L

begins by fetching the reset interrupt service vector at the reset vector address

FFFF00h (IVPD:FFFFh). RESET affects various registers and status bits.

General-Purpose I/O Pins

General-purpose configurable inputs/outputs. GPIO[7:0] can be individually

configured as inputs or outputs via the GPIO Direction Register (IODIR). Data can

be read from inputs or written to outputs via the GPIO Data Register (IODATA). The

GPIO pins are configured as inputs after reset.

Boot mode selection signals. GPIO[2:0]/BOOTM[2:0] are sampled following reset

to configure the boot mode for the DSP. After the boot is completed, these pins can

be used as general-purpose inputs/outputs.

The GPIO4 pin is also used as an output for handshaking purposes on some of the

boot modes. Although this pin is not involved in boot mode selection, users should

be aware that this pin will become active as an output during the bootload process

and should design accordingly. After the bootload process is complete, the loaded

application may change the function of the GPIO4 pin.

Multiplexed general-purpose input/output pins. The GPIO3 signal is multiplexed

with the CLKX2 signal through the SP0 pin. The function of the SP0 pin is

determined by the state of the GPIO7 pin during reset. The SP0 pin is set to GPIO3

if GPIO7 is low during reset. The SP0 pin is set to CLKX2 if GPIO7 is high during

reset. The function of the SP0 pin will be set once the device is taken out of reset

(RESET pin transitions from a low to high state).

The GPIO5 signal is multiplexed with the FSX2 signal through the SP2 pin. The

GPIO7

function of the SP2 pin is determined by the state of the GPIO7 pin during reset.

GPIO6

The SP2 pin is set to GPIO5 if GPIO7 is low during reset. The SP2 pin is set to

GPIO5

FSX2 if GPIO7 is high during reset. The function of the SP2 pin will be set once the

GPIO4

device is taken out of reset (RESET pin transitions from a low to high state).

I/O/Z

F, G, H, M

GPIO3

Input clock source selection. The CLKMD0 bit of the Clock Mode Control Register

GPIO2/BOOTM2

(CLKMD) determines which clock, either OSCOUT or X2/CLKIN, is used as an input

GPIO1/BOOTM1

clock source to the DSP. If GPIO4 is low at reset, the CLKMD0 bit of the Clock

GPIO0/BOOTM0

Mode Control Register (CLKMD) will be set to '0' and the internal oscillator and the

external crystal will generate an input clock (OSCOUT) for the DSP. If GPIO4 is

high, the CLKMD0 bit will be set to '1' and the input clock will be taken directly from

the X2/CLKIN pin.

An external crystal must be attached to the X1 and X2/CLKIN pins when the internal

oscillator is used to generate a clock to the DSP. Otherwise, when the oscillator is

not used to generate the input clock for the DSP, an externally generated 3.3-V

clock must be applied to the X2/CLKIN pin and the X1 pin must be left unconnected.

Function selection for multiplexed pins. The GPIO6 pin is used to select the

function of the multiplexed signals in the Parallel Port and the Host Port. The EMIF

will be disabled and the HPI will operate in non-multiplexed mode when the GPIO6

pin is low during reset. The EMIF will be enabled and the HPI will operate in

multiplexed mode when the GPIO6 pin is high during reset. The function of the

multiplexed signals will be set once the device is taken out of reset (RESET pin

transitions from a low to high state).

The GPIO7 pin is used to select the function of the multiplexed signals of Serial Port

2. The UART will be enabled and McBSP2 will be disabled when GPIO7 is low

during reset. McBSP2 will be enabled and the UART will be disalbed when GPIO7 is

high during reset. The function of the multiplexed signals will be set once the device

is taken out of reset (RESET pin transitions from a low to high state).

External output (latched software-programmable signal). XF is set high by the

BSET XF instruction, set low by BCLR XF instruction, or by loading ST1. XF is used

O/Z

for signaling other processors in multiprocessor configurations or used as a

general-purpose output pin. The XF pin is set to a value of '1' during reset.

Introduction

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