TMS320VC5502 datasheet(27/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 2-4. Signal Descriptions (continued)

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

EMIF output clock. ECLKOUT1 outputs the EMIF input clock by default but can be

held low or set to a high-impedance state through the EMIF Global Control

The ECLKOUT1 pin is always in a high-impedance state during reset. The behavior

of ECLKOUT1 immediately after reset depends on the state of GPIO6 during reset

and EMIFCLKS:

ECLKOUT1

O/Z

E, F, M

•

GPIO6 = 0 and EMIFCLKS =0: ECLKOUT1 is in a high-impendance state.

•

GPIO6 = 0 and EMIFCLKS =1: ECLKOUT1 toggles at ECLKIN frequency.

•

GPIO6 = 1 and EMIFCLKS =0: ECLKOUT1 toggles at SYSCLK3 frequency.

•

GPIO6 = 1 and EMIFCLKS =1: ECLKOUT1 toggles at ECLKIN frequency.

EMIF output clock. ECLKOUT2 can be enabled to output the EMIF input clock

divided by a factor 1, 2, or 4 through the EMIF Global Control Register 2 (EGCR2).

ECLKOUT2 can also be held low or set to a high-impedance state through the

EGCR2 register.

The ECLKOUT2 pin toggles with a clock frequency equal to the EMIF input clock

divided by 4 during reset. The behavior of ECLKOUT2 immediately after reset

depends on the state of GPIO6 during reset and EMIFCLKS:

ECLKOUT2

O/Z

E, F

•

GPIO6 = 0 and EMIFCLKS =0: ECLKOUT2 is held low.

•

GPIO6 = 0 and EMIFCLKS =1: ECLKOUT2 toggles at one-fourth of the ECLKIN

frequency.

•

GPIO6 = 1 and EMIFCLKS =0: ECLKOUT2 toggles at one-fourth of the

SYSCLK3 frequency.

•

GPIO6 = 1 and EMIFCLKS =1: ECLKOUT2 toggles at one-fourth of the ECLKIN

frequency.

EMIF input clock source select. The clock source for the EMIF is determined by

EMIFCLKS

C, L

the state of the EMIFCLKS pin. The EMIF uses an internal clock (SYSCLK3) if

EMIFCLKS is low. ECLKIN is used as the clock source if EMIFCLKS is high.

Host Port — Data Bus

The HD[7:0] pins of the Host Port serve one of two functions: parallel gen-

eral-purpose input/output (PGPIO) signals PGPIO[43:36] or host-port interface (HPI)

data bus signals HPI.HD[7:0]. The function of the HD[7:0] pins is determined by the

state of the GPIO6 pin during reset. The HD[7:0] pins are set to PGPIO[43:36] if

GPIO6 is low during reset. The HD[7:0] pins are set to HPI.HD[7:0] if GPIO6 is high

during reset. The function of the HD[7:0] pins will be set once the device is taken out

HD[7:0]

I/O/Z

of reset (RESET pin transitions from a low to high state).

The HD[7:0] bus includes bus holders to reduce the static power dissipation caused

by floating, unused pins. The bus holders also eliminate the need for external bias

resistors on unused pins. When the bus goes into a high-impedance state, the bus

C, D, F, G,

holders keep the address bus at the logic level that was most recently driven. The

H, M

bus holders are enabled at reset and can be enabled/disabled through the External

Bus Control Register (XBCR).

Parallel general-purpose I/O. PGPIO[43:36] is selected when GPIO6 is low during

PGPIO[43:36]

I/O/Z

reset. The PGPIO[43:36] signals are configured as inputs after reset.

Host data bus. HPI.HD[7:0] is selected when GPIO6 is high during reset. The

HPI.HD[7:0] signals are configured as inputs after reset.

HPI.HD[7:0]

I/O/Z

The HPI will operate in mulitplexed mode when GPIO6 is high during reset. In

multiplexed mode, an 8-bit data bus (HPI.HD[7:0]) carries both address and data.

Each host cycle on the bus consists of two consecutive 8-bit transfers.

Introduction

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