TMS320VC5502 datasheet(28/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 2-4. Signal Descriptions (continued)

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

Host Port — Control Pins

The HC0 pin of the Host Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO44 or host-port interface (HPI) signal HPI.HAS.

The function of the HC0 pin is determined by the state of the GPIO6 pin during

HC0

I/O/Z

reset. The HC0 pin is set to PGPIO44 if GPIO6 is low during reset. The HC0 pin is

set to HPI.HAS if GPIO6 is high during reset. The function of the HC0 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high

state).

C, F, G, H,

J, M

Parallel general-purpose I/O. PGPIO44 is selected when GPIO6 is low during

PGPIO44

I/O/Z

reset. The PGPIO44 signal is configured as an input after reset.

Host address strobe. HPI.HAS is selected when GPIO6 is high during reset. The

HPI.HAS signal is configured as an input after reset.

HPI.HAS

Hosts with multiplexed address and data pins may require HPI.HAS to latch the

address in the HPIA register. HPI.HAS is only available when the HPI is operating in

multiplexed mode.

The HC1 pin of the Host Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO45 or host-port interface (HPI) signal HPI.HBIL.

The function of the HC1 pin is determined by the state of the GPIO6 pin during

HC1

I/O/Z

reset. The HC1 pin is set to PGPIO45 if GPIO6 is low during reset. The HC1 pin is

set to HPI.HBIL if GPIO6 is high during reset. The function of the HC1 pin will be set

once the device is taken out of reset (RESET pin transitions from a low to high

F, G, H, K, state).

Parallel general-purpose I/O. PGPIO45 is selected when GPIO6 is low during

PGPIO45

I/O/Z

reset. The PGPIO45 signal is configured as an input after reset.

Host byte identification. HPI.HBIL is selected when GPIO6 is high during reset.

The HPI.HBIL signal is configured as an input after reset.

HPI.HBIL

In multiplexed mode, the host must use HPI.HBIL to identify the first and second

bytes of the host cycle.

HPI Pins

HCNTL0

HPI access control pins.The four binary states of the HCNTL0 and HCNTL1 pins

F, G, H, J, determine which HPI register is being accessed by the host (HPIC, HPID with

I/O/Z

autoincrementing, HPIA, or HPID). The HCNTL0 and HCNTL1 pins are configured

HCNTL1

as inputs after reset.

HPI chip-select. HCS must be low for the HPI to be selected by the host. The HCS

C, F, G, H, pin is configured as an input after reset.

HCS

I/O/Z

J, M

A host must not initiate transfer requests until the HPI has been brought out of reset,

see Section 3.8, Host-Port Interface (HPI), for more details.

F, G, H, J, Host read- or write-select. HR/W indicates whether the current access is to be a

HR/W

I/O/Z

read or write operation. The HR/W pin is configured as an input after reset.

HDS1

Host data strobe pins. The HDS1 and HDS2 pins are used for strobing data in and

out of the HPI. The HDS1 and HDS2 pins are configured as inputs after reset.

C, G, H, J

A host must not initiate transfer requests until the HPI has been brought out of reset,

HDS2

see Section 3.8, Host-Port Interface (HPI), for more details.

Host ready (from DSP to host). The HRDY pin informs the host when the HPI is

HRDY

O/Z

F, J, M

ready for the next transfer. The HRDY pin is in a high-impedance state during reset

and is set to output after reset with an output value of 1.

Host interrupt (from DSP to host). The HINT pin is used by the DSP to interrupt

F, G, H, J,

HINT

O/Z

the host. The HINT signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

HPI enable. The HPIENA pin must be driven high to enable the HPI for operation. If

the HPIENA pin is low, the HPI will be completely disabled and all HPI output pins

HPIENA

C, L

will be in a high-impedance state.

If the HPI is not needed, the HPIENA pin can be pulled low.

Interrupt and Reset Pins

Maskable external interrupts. INT0–INT3 are maskable interrupts. They are

enabled through the Interrupt Enable Registers (IER0 and IER1). All maskable

INT[3:0]

C, L

interrupts are globally enabled/disabled through the Interrupt Mode bit (INTM in

ST1_55). INT0–INT3 can be polled and reset via the Interrupt Flag Registers (IFR0

and IFR1). All interrupts are prioritized as shown in Table 3-77, Interrupt Table.

Introduction

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